mirror of https://github.com/m-labs/artiq
340 lines
13 KiB
Python
Executable File
340 lines
13 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi)
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from artiq import __version__ as artiq_version
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 10 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=50, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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# The default user SMA voltage on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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_sma33_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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]
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_ams101_dac = [
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("ams101_dac", 0,
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Subsignal("ldac", Pins("XADC:GPIO0")),
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Subsignal("clk", Pins("XADC:GPIO1")),
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Subsignal("mosi", Pins("XADC:GPIO2")),
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Subsignal("cs_n", Pins("XADC:GPIO3")),
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IOStandard("LVTTL")
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)
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]
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class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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AMPSoC.__init__(self)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0),
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self.platform.request("user_led", 1)))
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self.csr_devices.append("leds")
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_DDS"] = None
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.rtio_crg.cd_rtio.clk.attr.add("keep")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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class NIST_CLOCK(_NIST_Ions):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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rtio_channels = []
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for i in range(16):
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if i % 4 == 3:
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(2):
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phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 11
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class NIST_QC2(_NIST_Ions):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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clock_generators = []
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# All TTL channels are In+Out capable
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for i in range(40):
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phy = ttl_serdes_7series.Inout_8X(
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platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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for i in range(2):
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phy = ttl_simple.ClockGen(
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platform.request("clkout", i))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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# user SMA on KC705 board
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# AMS101 DAC on KC705 XADC header - optional
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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# add clock generators after RTIO_REGULAR_TTL_COUNT
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rtio_channels += clock_generators
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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for i in range(4):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 2
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self.config["DDS_CHANNELS_PER_BUS"] = 12
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for backplane_offset in range(2):
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phy = dds.AD9914(
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platform.request("dds", backplane_offset), 12, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / single-FPGA KC705-based "
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"systems with AD9 DDS (NIST Ions hardware)")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-H", "--hw-adapter", default="nist_clock",
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help="hardware adapter type: "
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"nist_clock/nist_qc2 "
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"(default: %(default)s)")
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args = parser.parse_args()
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hw_adapter = args.hw_adapter.lower()
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if hw_adapter == "nist_clock":
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cls = NIST_CLOCK
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elif hw_adapter == "nist_qc2":
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cls = NIST_QC2
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else:
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raise SystemExit("Invalid hardware adapter string (-H/--hw-adapter)")
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soc = cls(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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