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mirror of https://github.com/m-labs/artiq.git synced 2025-02-02 13:50:20 +08:00
artiq/artiq/gateware/targets
2018-03-29 10:20:31 +08:00
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__init__.py package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
kasli.py kasli: fix DRTIO master clock constraint 2018-03-29 10:20:31 +08:00
kc705.py ad53xx: port monitor, moninj dashboard, kc705 target 2018-03-24 16:04:02 +01:00
sayma_amc.py sayma: remove debug leftover 2018-03-29 10:20:17 +08:00
sayma_rtm.py sayma_rtm: fix serwb timing constraints (was causing the gated clock warning) 2018-03-12 11:25:29 +01:00