mirror of https://github.com/m-labs/artiq.git
38 lines
1.4 KiB
Python
38 lines
1.4 KiB
Python
from migen import *
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from misoc.interconnect import stream
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from artiq.gateware.serwb.packet import Depacketizer, Packetizer
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from artiq.gateware.serwb.etherbone import Etherbone
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class SERWBCore(Module):
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def __init__(self, phy, clk_freq, mode):
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self.submodules.etherbone = etherbone = Etherbone(mode)
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depacketizer = Depacketizer(clk_freq)
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packetizer = Packetizer()
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self.submodules += depacketizer, packetizer
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tx_cdc = stream.AsyncFIFO([("data", 32)], 8)
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tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(tx_cdc)
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self.submodules += tx_cdc
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rx_cdc = stream.AsyncFIFO([("data", 32)], 8)
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rx_cdc = ClockDomainsRenamer({"write": "serdes", "read": "sys"})(rx_cdc)
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self.submodules += rx_cdc
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self.comb += [
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# core <--> etherbone
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depacketizer.source.connect(etherbone.sink),
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etherbone.source.connect(packetizer.sink),
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# core --> serdes
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packetizer.source.connect(tx_cdc.sink),
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If(tx_cdc.source.stb & phy.init.ready,
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phy.serdes.tx_data.eq(tx_cdc.source.data)
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),
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tx_cdc.source.ack.eq(phy.init.ready),
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# serdes --> core
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rx_cdc.sink.stb.eq(phy.init.ready),
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rx_cdc.sink.data.eq(phy.serdes.rx_data),
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rx_cdc.source.connect(depacketizer.sink),
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]
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