mirror of https://github.com/m-labs/artiq.git
71 lines
2.6 KiB
Python
71 lines
2.6 KiB
Python
from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.wrpll.si549 import Si549
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from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
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from artiq.gateware.drtio.wrpll import thls, filters
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self):
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self.counter = CSRStatus(32)
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self.start = CSR()
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self.stop = CSR()
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ps_start = PulseSynchronizer("sys", "helper")
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ps_stop = PulseSynchronizer("sys", "helper")
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self.submodules += ps_start, ps_stop
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self.comb += [
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ps_start.i.eq(self.start.re & self.start.r),
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ps_stop.i.eq(self.stop.re & self.stop.r)
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]
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counter = Signal(32)
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self.specials += MultiReg(counter, self.counter.status)
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counting = Signal()
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self.sync.helper += [
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If(counting, counter.eq(counter + 1)),
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If(ps_start.o,
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counter.eq(0),
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counting.eq(1)
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),
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If(ps_stop.o, counting.eq(0))
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]
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class WRPLL(Module, AutoCSR):
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def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15):
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self.helper_reset = CSRStorage(reset=1)
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self.clock_domains.cd_helper = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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self.specials += [
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Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
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o_O=self.cd_helper.clk),
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_frequency = FrequencyCounter() # for diagnostics
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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helper_cd = ClockDomainsRenamer("helper")
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self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48))
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self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48))
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self.comb += [
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self.helper_dcxo.adpll_stb.eq(self.filter_helper.output_stb),
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self.helper_dcxo.adpll.eq(self.filter_helper.output),
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self.main_dcxo.adpll_stb.eq(self.filter_main.output_stb),
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self.main_dcxo.adpll.eq(self.filter_main.output)
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]
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