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Marius Weber
407fba232d
The suitable PFD clock depends on the use case and will likely need to be configured by some users. All things being equal, a higher PFD clock is desirable as is results in lower local oscillator phase-noise. Phaser was designed around a maximum PFD clock of 62.5 MHz. In integer mode, with no local oscillator frequency divisor set, a 62.5 MHz PFD clock results in a 125 MHz local oscillator step size. Given the +-200 MHz range of the DUC (more if using the DAC mixer), this step size will be acceptable to many. This seems like the most appropreate default configuration as it should offer the best phase-noise performance. Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk> |
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| applets | ||
| browser | ||
| compiler | ||
| coredevice | ||
| dashboard | ||
| examples | ||
| firmware | ||
| frontend | ||
| gateware | ||
| gui | ||
| language | ||
| master | ||
| sim | ||
| test | ||
| wavesynth | ||
| __init__.py | ||
| _version.py | ||
| appdirs.py | ||
| build_soc.py | ||
| experiment.py | ||
| remoting.py | ||
| tools.py | ||