mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-05 09:46:36 +08:00
Robert Jordens
4a0eaf0f95
gateware: add jesd204b awg gateware: copy phaser (df3825a) dsp/tools: update satadd mixin phaser: no DDS stubs dsp: accu fix phaser: cleanup/reduce sawg: kernel support and docs sawg: coredevice api fixes sawg: example ddb/experiment phaser: add conda package examples/phaser: typo sawg: adapt tests, fix accu stb sawg: tweak dds parameters sawg: move/adapt/extend tests sawg: test phy, refactor phaser: non-rtio spi phaser: target cli update phaser: ad9154-fmc-ebz pins phaser: reorganize fmc signal naming phaser: add test mode stubs phaser: txen is LVTTL phaser: clk spi xfer test phaser: spi for ad9154 and ad9516 phaser: spi tweaks ad9154: add register map from ad9144.xml ad9516: add register map from ad9517.xml and manual adaptation ad9154_reg: just generate getter/setter macros as well ad9154: reg WIP ad9154: check and fix registers kc705: single ended rtio_external_clk use single ended user_sma_clk_n instead of p/n to free up one clock sma kc705: mirror clk200 at user_sma_clock_p ad9516_regs.h: fix B_COUNTER_MSB phase: wire up clocking differently needs patched misoc kc705: feed rtio_external_clock directly kc705: remove rtio_external_clk for phaser phaser: spi tweaks ad9516: some startup ad9516_reg fixes phaser: setup ad9516 for supposed 500 MHz operation ad9516: use full duplex spi ad9154_reg: add CONFIG_REG_2 ad9154_reg: fixes phaser: write some ad9154 config ad9154_reg: fixes ad9154: more init, and human readable setup ad9154/ad9516: merge spi support ad9154: status readout Revert "kc705: remove rtio_external_clk for phaser" This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366. Revert "kc705: feed rtio_external_clock directly" This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5. Revert "phase: wire up clocking differently" This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc. Revert "kc705: mirror clk200 at user_sma_clock_p" This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba. Revert "kc705: single ended rtio_external_clk" This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf. ad9516: 2000 MHz clock phaser: test clock dist phaser: test freqs ad9154: iostandards phaser: drop clock monitor phaser: no separate i2c phaser: drive rtio from refclk, wire up sysref phaser: ttl channel for sync ad9154: 4x interp, status, tweaks phaser: sync/sysref 33V banks phaser: sync/sysref LVDS_25 inputs are VCCO tolerant phaser: user input-only ttls phaser: rtio fully from refclk ad9154: reg name usage fix ad9154: check register modifications Revert "ad9154: check register modifications" This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564. ad9154: fix status code ad9154: addrinc, recal serdes pll phaser: coredevice, example tweaks sawg: missing import sawg: type fixes ad9514: move setup functions ad9154: msb first also decreasing addr phaser: use sys4x for rtio internal ref phaser: move init code to main phaser: naming cleanup phaser: cleanup pins phaser: move spi to kernel cpu phaser: kernel support for ad9154 spi ad9154: add r/w methods ad9154: need return annotations ad9154: r/w methods are kernels ad9154_reg: portable helpers phaser: cleanup startup kernel ad9154: status test ad9154: prbs test ad9154: move setup, document phaser: more documentation
72 lines
2.5 KiB
Python
72 lines
2.5 KiB
Python
from migen.build.generic_platform import *
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fmc_adapter_io = [
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("ad9154_spi", 0,
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# AD9154 should give control of SPI to FMC when USB cable is unplugged,
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# It's the case, but the PIC18F24J50 is introducing noise on SPI SCK
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# (???) To workaround that, add 2 jumpers:
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# - on XP1, between pin 5 and 6 (will keep the PIC in reset)
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# - on JP3 (will force output enable on FXLA108)
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Subsignal("clk", Pins("HPC:LA03_P")),
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Subsignal("cs_n", Pins("HPC:LA04_N", "HPC:LA05_P")),
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Subsignal("mosi", Pins("HPC:LA03_N")),
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Subsignal("miso", Pins("HPC:LA04_P")),
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Subsignal("en", Pins("HPC:LA05_N")),
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IOStandard("LVTTL"),
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),
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("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVTTL")),
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("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVTTL")),
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("ad9154_refclk", 0,
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Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
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Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
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),
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("ad9154_sysref", 0,
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Subsignal("p", Pins("HPC:LA00_CC_P")),
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Subsignal("n", Pins("HPC:LA00_CC_N")),
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IOStandard("LVDS_25"),
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),
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("ad9154_sync", 0,
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Subsignal("p", Pins("HPC:LA01_CC_P")),
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Subsignal("n", Pins("HPC:LA01_CC_N")),
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IOStandard("LVDS_25"),
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),
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("ad9154_sync", 1,
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Subsignal("p", Pins("HPC:LA02_P")),
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Subsignal("n", Pins("HPC:LA02_N")),
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IOStandard("LVDS_25"),
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),
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("ad9154_jesd", 0, # AD9154's SERIND7
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Subsignal("txp", Pins("HPC:DP0_C2M_P")),
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Subsignal("txn", Pins("HPC:DP0_C2M_N"))
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),
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("ad9154_jesd", 1, # AD9154's SERIND6
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Subsignal("txp", Pins("HPC:DP1_C2M_P")),
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Subsignal("txn", Pins("HPC:DP1_C2M_N"))
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),
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("ad9154_jesd", 2, # AD9154's SERIND5
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Subsignal("txp", Pins("HPC:DP2_C2M_P")),
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Subsignal("txn", Pins("HPC:DP2_C2M_N"))
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),
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("ad9154_jesd", 3, # AD9154's SERIND4
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Subsignal("txp", Pins("HPC:DP3_C2M_P")),
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Subsignal("txn", Pins("HPC:DP3_C2M_N"))
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),
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("ad9154_jesd", 4, # AD9154's SERIND2
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Subsignal("txp", Pins("HPC:DP4_C2M_P")),
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Subsignal("txn", Pins("HPC:DP4_C2M_N"))
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),
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("ad9154_jesd", 5, # AD9154's SERIND0
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Subsignal("txp", Pins("HPC:DP5_C2M_P")),
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Subsignal("txn", Pins("HPC:DP5_C2M_N"))
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),
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("ad9154_jesd", 6, # AD9154's SERIND1
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Subsignal("txp", Pins("HPC:DP6_C2M_P")),
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Subsignal("txn", Pins("HPC:DP6_C2M_N"))
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),
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("ad9154_jesd", 7, # AD9154's SERIND3
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Subsignal("txp", Pins("HPC:DP7_C2M_P")),
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Subsignal("txn", Pins("HPC:DP7_C2M_N"))
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),
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]
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