mirror of https://github.com/m-labs/artiq.git
104 lines
3.1 KiB
Rust
104 lines
3.1 KiB
Rust
use board_misoc::{csr, clock};
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use core::slice;
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use byteorder::{ByteOrder, BigEndian};
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const CCLK_BIT: u8 = 1 << 0;
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const DIN_BIT: u8 = 1 << 1;
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const DONE_BIT: u8 = 1 << 2;
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const INIT_B_BIT: u8 = 1 << 3;
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const PROGRAM_B_BIT: u8 = 1 << 4;
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const GATEWARE: *mut u8 = csr::CONFIG_SLAVE_FPGA_GATEWARE as *mut u8;
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unsafe fn shift_u8(data: u8) {
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for i in 0..8 {
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let mut bits: u8 = PROGRAM_B_BIT;
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if data & (0x80 >> i) != 0 {
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bits |= DIN_BIT;
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}
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// Without delays, this is about 6 MHz CCLK which is fine.
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csr::slave_fpga_cfg::out_write(bits);
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// clock::spin_us(1);
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csr::slave_fpga_cfg::out_write(bits | CCLK_BIT);
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// clock::spin_us(1);
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}
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}
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pub fn prepare() -> Result<(), &'static str> {
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unsafe {
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if csr::slave_fpga_cfg::in_read() & DONE_BIT != 0 {
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info!(" DONE before loading");
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}
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
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info!(" INIT asserted before loading");
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}
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csr::slave_fpga_cfg::out_write(0);
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csr::slave_fpga_cfg::oe_write(CCLK_BIT | DIN_BIT | PROGRAM_B_BIT);
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clock::spin_us(1_000); // TPROGRAM=250ns min, be_generous
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT != 0 {
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return Err("Did not assert INIT in reaction to PROGRAM");
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}
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csr::slave_fpga_cfg::out_write(PROGRAM_B_BIT);
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clock::spin_us(10_000); // TPL=5ms max
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
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return Err("Did not exit INIT after releasing PROGRAM");
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}
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if csr::slave_fpga_cfg::in_read() & DONE_BIT != 0 {
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return Err("DONE high despite PROGRAM");
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}
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}
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Ok(())
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}
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pub fn input(data: &[u8]) -> Result<(), &'static str> {
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unsafe {
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for i in data {
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shift_u8(*i);
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if csr::slave_fpga_cfg::in_read() & INIT_B_BIT == 0 {
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return Err("INIT asserted during load");
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}
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}
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}
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Ok(())
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}
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pub fn complete() -> Result<(), &'static str> {
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unsafe {
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let t = clock::get_ms();
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while csr::slave_fpga_cfg::in_read() & DONE_BIT == 0 {
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if clock::get_ms() > t + 100 {
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return Err("Timeout wating for DONE after loading");
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}
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shift_u8(0xff);
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}
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shift_u8(0xff); // "Compensate for Special Startup Conditions"
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csr::slave_fpga_cfg::out_write(PROGRAM_B_BIT);
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csr::slave_fpga_cfg::oe_write(PROGRAM_B_BIT);
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}
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Ok(())
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}
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pub fn load() -> Result<(), &'static str> {
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info!("Loading slave FPGA gateware...");
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let header = unsafe { slice::from_raw_parts(GATEWARE, 8) };
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let magic = BigEndian::read_u32(&header[0..]);
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let length = BigEndian::read_u32(&header[4..]) as usize;
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info!(" magic: 0x{:08x}, length: 0x{:08x}", magic, length);
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if magic != 0x5352544d { // "SRTM", see sayma_rtm target as well
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return Err("Bad magic");
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}
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if length > 0x220000 {
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return Err("Too large (corrupted?)");
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}
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prepare()?;
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input(unsafe { slice::from_raw_parts(GATEWARE.offset(8), length) })?;
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complete()?;
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info!(" ...done");
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Ok(())
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}
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