mirror of https://github.com/m-labs/artiq.git
226 lines
8.0 KiB
Python
226 lines
8.0 KiB
Python
from migen import *
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from migen.genlib.io import *
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from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.cores.code_8b10b import Encoder, Decoder
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def K(x, y):
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return (y << 5) | x
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class _S7SerdesClocking(Module):
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def __init__(self, pads, mode="master"):
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self.refclk = Signal()
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# # #
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# In Master mode, generate the linerate/10 clock. Slave will re-multiply it.
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if mode == "master":
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converter = stream.Converter(40, 8)
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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converter.sink.data.eq(Replicate(Signal(10, reset=0b1111100000), 4)),
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]
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=self.refclk,
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i_OCE=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D1=converter.source.data[0], i_D2=converter.source.data[1],
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i_D3=converter.source.data[2], i_D4=converter.source.data[3],
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i_D5=converter.source.data[4], i_D6=converter.source.data[5],
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i_D7=converter.source.data[6], i_D8=converter.source.data[7]
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),
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DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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]
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# In Slave mode, multiply the clock provided by Master with a PLL/MMCM
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elif mode == "slave":
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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class _S7SerdesTX(Module):
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def __init__(self, pads, mode="master"):
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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# # #
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# 8b10b encoder
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self.submodules.encoder = encoder = CEInserter()(Encoder(4, True))
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self.comb += encoder.ce.eq(ce)
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# 40 --> 8 converter
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converter = stream.Converter(40, 8)
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter accepts the 40 bits
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ce.eq(converter.sink.ack),
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# If not idle, connect encoder to converter
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If(~idle,
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converter.sink.data.eq(Cat(*[encoder.output[i] for i in range(4)]))
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),
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# If comma, send K28.5
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If(comma,
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encoder.k[0].eq(1),
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encoder.d[0].eq(K(28,5)),
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# Else connect TX to encoder
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).Else(
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encoder.k[0].eq(k[0]),
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encoder.k[1].eq(k[1]),
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encoder.k[2].eq(k[2]),
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encoder.k[3].eq(k[3]),
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encoder.d[0].eq(d[0:8]),
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encoder.d[1].eq(d[8:16]),
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encoder.d[2].eq(d[16:24]),
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encoder.d[3].eq(d[24:32])
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)
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]
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# Data output (DDR with sys4x)
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data = Signal()
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_SERDES_MODE="MASTER",
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o_OQ=data,
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i_OCE=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D1=converter.source.data[0], i_D2=converter.source.data[1],
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i_D3=converter.source.data[2], i_D4=converter.source.data[3],
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i_D5=converter.source.data[4], i_D6=converter.source.data[5],
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i_D7=converter.source.data[6], i_D8=converter.source.data[7]
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),
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DifferentialOutput(data, pads.tx_p, pads.tx_n)
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]
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class _S7SerdesRX(Module):
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def __init__(self, pads, mode="master"):
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# Control
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self.delay_rst = Signal()
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self.delay_inc = Signal()
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self.bitslip_value = bitslip_value = Signal(6)
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# Status
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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# # #
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# Data input (DDR with sys4x)
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data_nodelay = Signal()
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data_delayed = Signal()
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data_deserialized = Signal(8)
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self.specials += [
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DifferentialInput(pads.rx_p, pads.rx_n, data_nodelay),
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Instance("IDELAYE2",
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p_DELAY_SRC="IDATAIN", p_SIGNAL_PATTERN="DATA",
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p_CINVCTRL_SEL="FALSE", p_HIGH_PERFORMANCE_MODE="TRUE",
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p_REFCLK_FREQUENCY=200.0, p_PIPE_SEL="FALSE",
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p_IDELAY_TYPE="VARIABLE", p_IDELAY_VALUE=0,
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i_C=ClockSignal(),
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i_LD=self.delay_rst,
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i_CE=self.delay_inc,
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i_LDPIPEEN=0, i_INC=1,
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i_IDATAIN=data_nodelay, o_DATAOUT=data_delayed
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),
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Instance("ISERDESE2",
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p_DATA_WIDTH=8, p_DATA_RATE="DDR",
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p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
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p_NUM_CE=1, p_IOBDELAY="IFD",
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i_DDLY=data_delayed,
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i_CE1=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"),
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i_CLKDIV=ClockSignal("sys"),
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i_BITSLIP=0,
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o_Q8=data_deserialized[0], o_Q7=data_deserialized[1],
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o_Q6=data_deserialized[2], o_Q5=data_deserialized[3],
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o_Q4=data_deserialized[4], o_Q3=data_deserialized[5],
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o_Q2=data_deserialized[6], o_Q1=data_deserialized[7]
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)
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]
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# 8 --> 40 converter and bitslip
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converter = stream.Converter(8, 40)
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self.submodules += converter
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bitslip = CEInserter()(BitSlip(40))
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self.submodules += bitslip
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter outputs the 40 bits
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ce.eq(converter.source.stb),
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# Connect input data to converter
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converter.sink.data.eq(data_deserialized),
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# Connect converter to bitslip
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bitslip.ce.eq(ce),
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bitslip.value.eq(bitslip_value),
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bitslip.i.eq(converter.source.data)
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]
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# 8b10b decoder
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self.submodules.decoders = decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
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self.comb += [decoders[i].ce.eq(ce) for i in range(4)]
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self.comb += [
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# Connect bitslip to decoder
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decoders[0].input.eq(bitslip.o[0:10]),
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decoders[1].input.eq(bitslip.o[10:20]),
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decoders[2].input.eq(bitslip.o[20:30]),
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decoders[3].input.eq(bitslip.o[30:40]),
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# Connect decoder to output
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self.k.eq(Cat(*[decoders[i].k for i in range(4)])),
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self.d.eq(Cat(*[decoders[i].d for i in range(4)])),
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]
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# Status
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idle_timer = WaitTimer(256)
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self.submodules += idle_timer
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self.comb += [
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idle_timer.wait.eq(1),
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self.idle.eq(idle_timer.done &
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((bitslip.o == 0) | (bitslip.o == (2**40-1)))),
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self.comma.eq(
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(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
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(decoders[1].k == 0) & (decoders[1].d == 0) &
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(decoders[2].k == 0) & (decoders[2].d == 0) &
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(decoders[3].k == 0) & (decoders[3].d == 0))
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]
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@ResetInserter()
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class S7Serdes(Module):
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def __init__(self, pads, mode="master"):
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self.submodules.clocking = _S7SerdesClocking(pads, mode)
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self.submodules.tx = _S7SerdesTX(pads, mode)
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self.submodules.rx = _S7SerdesRX(pads, mode)
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