mirror of https://github.com/m-labs/artiq
71 lines
1.5 KiB
Python
71 lines
1.5 KiB
Python
import numpy as np
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from operator import or_
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.rtio.phy.sawg import Channel
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from .tools import rtio_xfer
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def pack_tri(port, *v):
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r = 0
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w = 0
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for vi, p in zip(v, port.payload.flatten()):
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w += len(p)
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r |= int(vi*(1 << w))
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return r
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def gen_rtio(dut):
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yield
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yield from rtio_xfer(
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dut,
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a1=pack_tri(dut.a1.a, .1),
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f0=pack_tri(dut.b.f, .01234567),
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f1=pack_tri(dut.a1.f, .01234567),
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a2=pack_tri(dut.a1.a, .05),
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f2=pack_tri(dut.a1.f, .00534567),
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)
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def gen_log(dut, o, n):
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for i in range(3 + dut.latency):
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yield
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for i in range(n):
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yield
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o.append((yield from [(yield _) for _ in dut.o]))
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#o.append([(yield dut.a1.xo[0])])
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def _test_channel():
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width = 16
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dut = ClockDomainsRenamer({"rio_phy": "sys"})(
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Channel(width=width, parallelism=4)
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)
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if False:
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print(convert(dut))
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return
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o = []
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run_simulation(
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dut,
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[gen_rtio(dut), gen_log(dut, o, 128)],
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vcd_name="dds.vcd")
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o = np.array(o)/(1 << (width - 1))
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o = o.ravel()
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np.savez_compressed("dds.npz", o=o)
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import matplotlib.pyplot as plt
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fig, ax = plt.subplots(2)
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ax[0].step(np.arange(o.size), o)
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ax[1].psd(o, 1 << 10, Fs=1, noverlap=1 << 9, scale_by_freq=False)
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fig.savefig("dds.pdf")
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plt.show()
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if __name__ == "__main__":
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_test_channel()
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