mirror of https://github.com/m-labs/artiq
37 lines
869 B
Python
37 lines
869 B
Python
import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp import sawg
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from artiq.gateware.test.dsp.tools import xfer
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def _test_gen_dds(dut, o):
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yield from xfer(dut,
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a=dict(a0=10),
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p=dict(a0=0),
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f=dict(a0=1),
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)
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for i in range(256//dut.parallelism):
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yield
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o.append((yield from [(yield _) for _ in dut.xo]))
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def _test_channel():
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widths = sawg._Widths(t=8, a=4*8, p=8, f=16)
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orders = sawg._Orders(a=4, p=1, f=2)
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dut = sawg.SplineParallelDDS(widths, orders, parallelism=2)
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if False:
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print(convert(dut))
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else:
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o = []
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run_simulation(dut, _test_gen_dds(dut, o), vcd_name="dds.vcd")
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o = np.array(o)
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print(o[:, :])
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if __name__ == "__main__":
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_test_channel()
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