mirror of https://github.com/m-labs/artiq
185 lines
5.6 KiB
Python
185 lines
5.6 KiB
Python
core_addr = "192.168.1.70"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_moninj": {
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"type": "controller",
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"host": "::1",
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"port_proxy": 1383,
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"port": 1384,
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"command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 0}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 2}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 3}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 4}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 5}
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},
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urukul0_cpld={
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"refclk": 150e6,
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"clk_sel": 2
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}
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}
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)
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for i in range(4):
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device_db["urukul0_ch" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 16, # 600MHz sample rate
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"pll_vco": 2,
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"chip_select": 4 + i,
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"cpld_device": "urukul0_cpld",
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"sw_device": "ttl_urukul0_sw" + str(i)
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}
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}
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"""
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artiq_route routing.bin init
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artiq_route routing.bin set 0 0
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artiq_route routing.bin set 1 1 0
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artiq_route routing.bin set 2 1 1 0
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artiq_route routing.bin set 3 2 0
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artiq_route routing.bin set 4 2 1 0
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artiq_coremgmt -D kasli config write -f routing_table routing.bin
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"""
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for sayma in range(2):
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amc_base = 0x010000 + sayma*0x020000
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rtm_base = 0x020000 + sayma*0x020000
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for i in range(4):
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device_db["led" + str(4*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": amc_base + i}
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}
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for i in range(2):
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device_db["ttl_mcx" + str(2*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": amc_base + 4 + i}
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}
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for i in range(8):
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device_db["sawg" + str(8*sayma+i)] = {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": amc_base + 6 + i*10, "parallelism": 4}
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}
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for basemod in range(2):
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for i in range(4):
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device_db["sawg_sw" + str(8*sayma+4*basemod+i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + i}
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}
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att_idx = 2*sayma + basemod
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device_db["basemod_att_rst_n"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 4}
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}
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device_db["basemod_att_clk"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 5}
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}
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device_db["basemod_att_le"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 6}
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}
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device_db["basemod_att_mosi"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": rtm_base + basemod*9 + 7}
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}
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device_db["basemod_att_miso"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": rtm_base + basemod*9 + 8}
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}
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device_db["basemod_att"+str(att_idx)] = {
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"type": "local",
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"module": "artiq.coredevice.basemod_att",
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"class": "BaseModAtt",
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"arguments": {
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"rst_n": "basemod_att_rst_n"+str(att_idx),
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"clk": "basemod_att_clk"+str(att_idx),
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"le": "basemod_att_le"+str(att_idx),
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"mosi": "basemod_att_mosi"+str(att_idx),
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"miso": "basemod_att_miso"+str(att_idx),
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}
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}
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