artiq/artiq/gateware/targets
mwojcik 7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
..
__init__.py package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
kasli.py kasli: add SED lanes count option to HW description JSON file (#1745) 2021-12-03 17:05:35 +08:00
kasli_generic.py kasli: add SED lanes count option to HW description JSON file (#1745) 2021-12-03 17:05:35 +08:00
kc705.py kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
metlino.py gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
sayma_amc.py gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
sayma_rtm.py gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00