mirror of https://github.com/m-labs/artiq.git
80 lines
2.7 KiB
Python
80 lines
2.7 KiB
Python
from migen import *
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from artiq.gateware.rtio import rtlink
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class SimpleEdgeCounter(Module):
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"""Counts rising/falling edges of an input signal.
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Control (sensitivity/zeroing) is done via a single RTIO output channel,
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which is is also used to request an input event to be emitted with the
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current counter value.
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:param input_state: The (scalar) input signal to detect edges of. This
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should already be in the rio_phy clock domain.
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:param counter_width: The width of the counter register, in bits. Defaults
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to 31 to match integers being signed in ARTIQ Python.
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"""
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def __init__(self, input_state, counter_width=31):
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assert counter_width >= 2
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# RTIO interface:
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# - output 0: 4 bits, <count_rising><count_falling><send_event><zero_counter>
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# - input 0: 32 bits, accumulated edge count
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(4, enable_replace=False),
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rtlink.IInterface(counter_width))
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# # #
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current_count = Signal(counter_width)
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count_rising = Signal()
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count_falling = Signal()
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send_event_stb = Signal()
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zero_counter_stb = Signal()
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# Read configuration from RTIO output events.
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self.sync.rio += [
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If(self.rtlink.o.stb,
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count_rising.eq(self.rtlink.o.data[0]),
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count_falling.eq(self.rtlink.o.data[1]),
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send_event_stb.eq(self.rtlink.o.data[2]),
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zero_counter_stb.eq(self.rtlink.o.data[3])
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).Else(
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send_event_stb.eq(0),
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zero_counter_stb.eq(0)
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)
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]
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# Generate RTIO input event with current count if requested.
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event_data = Signal.like(current_count)
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self.comb += [
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self.rtlink.i.stb.eq(send_event_stb),
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self.rtlink.i.data.eq(event_data)
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]
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# Keep previous input state for edge detection.
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input_state_d = Signal()
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self.sync.rio_phy += input_state_d.eq(input_state)
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# Count input edges, saturating at the maximum.
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new_count = Signal.like(current_count)
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self.comb += new_count.eq(
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current_count + Mux(current_count == 2**counter_width - 1,
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0,
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(count_rising & (input_state & ~input_state_d)) |
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(count_falling & (~input_state & input_state_d))
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)
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)
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self.sync.rio += [
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event_data.eq(new_count),
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current_count.eq(Mux(zero_counter_stb, 0, new_count))
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]
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if __name__ == '__main__':
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input = Signal(name="input")
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print(fhdl.verilog.convert(SimpleEdgeCounter(input)))
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