mirror of https://github.com/m-labs/artiq.git
29 lines
991 B
Python
29 lines
991 B
Python
from migen import *
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from migen.genlib.cdc import *
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__all__ = ["GrayCodeTransfer"]
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# note: transfer is in rtio/sys domains and not affected by the reset CSRs
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class GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rtio domain
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self.o = Signal(width, reset_less=True) # in sys domain
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# # #
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# convert to Gray code
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value_gray_rtio = Signal(width, reset_less=True)
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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value_gray_rtio.attr.add("no_retiming")
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self.specials += MultiReg(value_gray_rtio, value_gray_sys)
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync += self.o.eq(value_sys)
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