mirror of https://github.com/m-labs/artiq
126 lines
4.1 KiB
Python
126 lines
4.1 KiB
Python
import unittest
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from migen import *
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from artiq.gateware.rtio.phy.ttl_serdes_generic import *
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class _FakeSerdes:
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def __init__(self):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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class _TB(Module):
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def __init__(self):
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self.serdes = _FakeSerdes()
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self.submodules.dut = ClockDomainsRenamer({"rio_phy": "sys", "rio": "sys"})(
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InOut(self.serdes))
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class TestTTLSerdes(unittest.TestCase):
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def test_input(self):
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tb = _TB()
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def gen():
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yield tb.dut.rtlink.o.address.eq(2)
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yield tb.dut.rtlink.o.data.eq(0b11)
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yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising + falling
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.oe), 0)
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self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
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yield tb.serdes.i.eq(0b11111110) # rising edge at fine_ts = 1
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 1)
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yield tb.serdes.i.eq(0b01111111) # falling edge at fine_ts = 7
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yield
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yield tb.serdes.i.eq(0b00000000)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 7)
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yield tb.serdes.i.eq(0b11000000) # rising edge at fine_ts = 6
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 6)
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yield tb.dut.rtlink.o.address.eq(2)
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yield tb.dut.rtlink.o.data.eq(0b01)
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yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising only
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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yield tb.serdes.i.eq(0b00001111) # falling edge at fine_ts = 4
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yield
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yield tb.serdes.i.eq(0b00000000)
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yield
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# no strobe, sensitivity is rising edge
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self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
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yield tb.serdes.i.eq(0b11110000) # rising edge at fine_ts = 4
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 4)
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run_simulation(tb, gen())
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def test_output(self):
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tb = _TB()
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def gen():
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yield tb.dut.rtlink.o.address.eq(1)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.stb.eq(1) # set Output Enable to 1
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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yield
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self.assertEqual((yield tb.serdes.oe), 1)
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yield tb.dut.rtlink.o.address.eq(0)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.fine_ts.eq(3)
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yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 3
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b11111000)
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yield
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self.assertEqual((yield tb.serdes.o), 0b11111111) # stays at 1
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yield tb.dut.rtlink.o.data.eq(0)
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yield tb.dut.rtlink.o.fine_ts.eq(0)
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yield tb.dut.rtlink.o.stb.eq(1) # falling edge at fine_ts = 0
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b00000000)
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yield
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self.assertEqual((yield tb.serdes.o), 0b00000000)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.fine_ts.eq(7)
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yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 7
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b10000000)
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run_simulation(tb, gen())
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