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mirror of https://github.com/m-labs/artiq.git synced 2024-12-05 09:46:36 +08:00
artiq/artiq
2015-08-17 15:45:08 +08:00
..
coredevice comm_tcp: enable TCP keepalive on host side as well 2015-08-15 16:03:00 +08:00
devices pxi6733: fix verification of the number of buffered sample values 2015-08-14 10:36:03 +02:00
frontend rpctool: use pprint 2015-08-17 15:45:08 +08:00
gateware rtio: detect collision errors 2015-07-29 19:43:35 +08:00
gui gui: save/restore state of pyqtgraph plots (closes #98) 2015-08-15 15:29:41 +08:00
language language/environment: support non-stored results 2015-08-06 18:43:27 +08:00
master scheduler: refactor, fix pipeline hazards 2015-08-10 21:58:11 +08:00
protocols pc_rpc: id_parameters -> description 2015-08-11 23:29:52 +08:00
py2llvm Fold llvmlite patches into m-labs/llvmlite repository. 2015-08-05 03:49:01 +03:00
sim refactor ddb/pdb/rdb 2015-07-13 22:21:32 +02:00
test scheduler: refactor, fix pipeline hazards 2015-08-10 21:58:11 +08:00
transforms expose machine units to user 2015-07-01 22:22:53 +02:00
wavesynth wavesynth/Synthesizer: allow empty data 2015-07-23 12:34:54 -06:00
__init__.py import DDS phase modes at the top level 2015-07-29 23:32:33 +08:00
tools.py scheduler: refactor, fix pipeline hazards 2015-08-10 21:58:11 +08:00