mirror of
https://github.com/m-labs/artiq.git
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Robert Jordens
01416bb0be
These are contributions of >= 30% or >= 20 lines (half-automated).
I hereby resubmit all my previous contributions to the ARTIQ project
under the following terms:
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Closes #130
Signed-off-by: Robert Jordens <jordens@gmail.com>
203 lines
8.5 KiB
Python
203 lines
8.5 KiB
Python
# Copyright (C) 2014, 2015 Robert Jordens <jordens@gmail.com>
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# Copyright (C) 2014, 2015 M-Labs Limited
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from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.pipistrello import BaseSoC
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, clk_freq):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtiox8 = ClockDomain(reset_less=True)
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self.rtiox4_stb = Signal()
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self.rtiox8_stb = Signal()
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rtio_f = 125*1000*1000
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f = Fraction(rtio_f, clk_freq)
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rtio_internal_clk = Signal()
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rtio_external_clk = Signal()
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pmt2 = platform.request("pmt", 2)
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dcm_locked = Signal()
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rtio_clk = Signal()
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pll_locked = Signal()
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pll = Signal(3)
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pll_fb = Signal()
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self.specials += [
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Instance("IBUFG", i_I=pmt2, o_O=rtio_external_clk),
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Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
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p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
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p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
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p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
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i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
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i_FREEZEDCM=0, i_RST=ResetSignal(), o_LOCKED=dcm_locked),
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Instance("BUFGMUX",
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i_I0=rtio_internal_clk, i_I1=rtio_external_clk,
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i_S=self._clock_sel.storage, o_O=rtio_clk),
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Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
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p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0,
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i_RST=self._pll_reset.storage | ~dcm_locked, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8,
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p_CLKFBOUT_PHASE=0., i_CLKINSEL=1,
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i_CLKIN1=rtio_clk, i_CLKIN2=0,
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p_CLKIN1_PERIOD=1e9/rtio_f, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_locked,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=1,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=2,
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p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=8),
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Instance("BUFPLL", p_DIVIDE=8,
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i_PLLIN=pll[0], i_GCLK=self.cd_rtio.clk,
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i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox8.clk,
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o_SERDESSTROBE=self.rtiox8_stb),
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Instance("BUFPLL", p_DIVIDE=4,
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i_PLLIN=pll[1], i_GCLK=self.cd_rtio.clk,
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i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox4.clk,
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o_SERDESSTROBE=self.rtiox4_stb),
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Instance("BUFG", i_I=pll[2], o_O=self.cd_rtio.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status),
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]
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# ISE infers correct period constraints for cd_rtio.clk from
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# the internal clock. The first two TIGs target just the BUFGMUX.
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platform.add_platform_command("""
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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NET "{ext_clk}" TNM_NET = "GRPext_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
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NET "{int_clk}" TNM_NET = "GRPint_clk";
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
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TIMESPEC "TSfix_ise3" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
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rtio_clk=self.cd_rtio.clk)
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class NIST_QC1(BaseSoC, AMPSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 13,
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"kernel_cpu": 14,
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"rtio_moninj": 15
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(l2_size=64*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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platform.toolchain.ise_commands += """
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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"""
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platform.add_extension(nist_qc1.papilio_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1),
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platform.request("user_led", 2),
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platform.request("user_led", 3),
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))
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
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# RTIO channels
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rtio_channels = []
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# pmt1 can run on a 8x serdes if pmt0 is not used
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for i in range(2):
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phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
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self.rtio_crg.rtiox4_stb)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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ofifo_depth=4))
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# ttl2 can run on a 8x serdes if xtrig is not used
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for i in range(15):
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if i in (0, 1):
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phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
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self.rtio_crg.rtiox4_stb)
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elif i in (2,):
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phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
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self.rtio_crg.rtiox8_stb)
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else:
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
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phy = ttl_simple.Output(platform.request("ext_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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phy = ttl_simple.Output(platform.request("user_led", 4))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
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self.add_constant("DDS_CHANNEL_COUNT", 8)
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self.add_constant("DDS_AD9858")
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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# RTIO core
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
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self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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# CPU connections
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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rtio_csrs)
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default_subtarget = NIST_QC1
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