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2e39802a61
artiq/artiq/gateware/rtio/phy
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Sebastien Bourdeauducq 2e39802a61 rtio/wishbone: make replace configurable
2016-03-10 09:44:05 +08:00
..
__init__.py rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
dds.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
spi.py rtio.spi: drop unused argument 2016-02-28 21:06:20 +01:00
ttl_serdes_7series.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
ttl_serdes_generic.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
ttl_serdes_spartan6.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
ttl_simple.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
wishbone.py rtio/wishbone: make replace configurable 2016-03-10 09:44:05 +08:00