mirror of https://github.com/m-labs/artiq.git
90 lines
2.5 KiB
Python
90 lines
2.5 KiB
Python
from functools import reduce
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from operator import xor
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from migen import *
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from misoc.interconnect import stream
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def K(x, y):
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return (y << 5) | x
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@ResetInserter()
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@CEInserter()
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class _Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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flip = reduce(xor, [curval[tap] for tap in taps])
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self.comb += self.o[i].eq(flip ^ self.i[i])
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curval.insert(0, flip)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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class Scrambler(Module):
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def __init__(self, sync_interval=2**10):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
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# # #
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# Scrambler
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self.submodules.scrambler = scrambler = _Scrambler(32)
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# Insert K29.7 SYNC character every "sync_interval" cycles
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count = Signal(max=sync_interval)
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self.sync += If(source.ack, count.eq(count + 1))
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self.comb += [
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source.stb.eq(1),
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If(count == 0,
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scrambler.reset.eq(1),
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source.k.eq(0b1),
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source.d.eq(K(29, 7)),
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).Else(
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If(sink.stb, scrambler.i.eq(sink.data)),
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source.k.eq(0),
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source.d.eq(scrambler.o),
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If(source.ack,
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sink.ack.eq(1),
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scrambler.ce.eq(1)
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)
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)
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]
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class Descrambler(Module):
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def __init__(self):
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self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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# Descrambler
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self.submodules.descrambler = descrambler = _Scrambler(32)
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self.comb += descrambler.i.eq(sink.d)
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# Detect K29.7 SYNC character and synchronize Descrambler
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self.comb += \
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If(sink.stb,
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If((sink.k == 0b1) & (sink.d == K(29,7)),
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sink.ack.eq(1),
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descrambler.reset.eq(1)
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).Else(
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source.stb.eq(1),
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source.data.eq(descrambler.o),
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If(source.ack,
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sink.ack.eq(1),
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descrambler.ce.eq(1)
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)
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)
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)
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