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mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 21:26:37 +08:00
artiq/artiq/gateware/serwb
2017-11-10 10:37:08 +01:00
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__init__.py gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
core.py gateware/serwb/core: cleanup and increase fifo depth 2017-11-10 10:33:39 +01:00
etherbone.py gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
kusphy.py gateware/serwb/kusphy: use locally inverted clk_b on iserdese3 2017-11-10 10:35:48 +01:00
packet.py gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
phy.py gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8 2017-11-10 10:37:08 +01:00
s7phy.py gateware/serwb: change serdes clock domain to serwb_serdes 2017-08-30 15:44:44 +02:00