mirror of https://github.com/m-labs/artiq.git
106 lines
4.5 KiB
Python
106 lines
4.5 KiB
Python
from migen import *
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from .adc_ser import ADC, ADCParams
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from .iir import IIR, IIRWidths
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from .dds_ser import DDS, DDSParams
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def predict_timing(adc_p, iir_p, dds_p):
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"""
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The following is a sketch of the timing for 1 Sampler (8 ADCs) and N Urukuls
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Shown here, the cycle duration is limited by the IIR loading+processing time.
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ADC|CONVH|CONV|READ|RTT|IDLE|CONVH|CONV|READ|RTT|IDLE|CONVH|CONV|READ|RTT|...
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|4 |57 |16 |8 | .. |4 |57 |16 |8 | .. |4 |57 |16 |8 |...
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---+-------------------+------------------------+------------------------+---
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IIR| |LOAD|PROC |SHIFT|LOAD|PROC |SHIFT|...
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| |8 |16*N+9 |16 |8 |16*N+9 |16 |...
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---+--------------------------------------+------------------------+---------
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DDS| |CMD|PROF|WAIT|IO_UP|IDLE|CMD|PR...
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| |16 |128 |1 |1 | .. |16 | ...
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IIR loading starts once the ADC presents its data, the DDSes are updated
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once the IIR processing is over. These are the only blocking processes.
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IIR shifting happens in parallel to writing to the DDSes and ADC conversions
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take place while the IIR filter is processing or the DDSes are being
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written to, depending on the cycle duration (given by whichever module
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takes the longest).
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"""
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t_adc = (adc_p.t_cnvh + adc_p.t_conv + adc_p.t_rtt +
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adc_p.channels*adc_p.width//adc_p.lanes) + 1
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# load adc_p.channels values, process dds_p.channels
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# (4 processing phases and 2 additional stages à 4 phases
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# to complete the processing of the last channel)
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t_iir = adc_p.channels + 4*dds_p.channels + 8 + 1
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t_dds = (dds_p.width*2 + 1)*dds_p.clk + 1
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t_cycle = max(t_adc, t_iir, t_dds)
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return t_adc, t_iir, t_dds, t_cycle
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class Servo(Module):
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def __init__(self, adc_pads, dds_pads, adc_p, iir_p, dds_p):
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t_adc, t_iir, t_dds, t_cycle = predict_timing(adc_p, iir_p, dds_p)
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assert t_iir + 2*adc_p.channels < t_cycle, "need shifting time"
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self.submodules.adc = ADC(adc_pads, adc_p)
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self.submodules.iir = IIR(iir_p)
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self.submodules.dds = DDS(dds_pads, dds_p)
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# adc channels are reversed on Sampler
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for iir, adc in zip(self.iir.adc, reversed(self.adc.data)):
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self.comb += iir.eq(adc)
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for dds, iir in zip(self.dds.profile, self.iir.dds):
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self.comb += dds.eq(iir)
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# If high, a new cycle is started if the current cycle (if any) is
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# finished. Consequently, if low, servo iterations cease after the
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# current cycle is finished. Don't care while the first step (ADC)
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# is active.
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self.start = Signal()
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# Counter for delay between end of ADC cycle and start of next one,
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# depending on the duration of the other steps.
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t_restart = t_cycle - t_adc + 1
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assert t_restart > 1
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cnt = Signal(max=t_restart)
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cnt_done = Signal()
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active = Signal(3)
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# Indicates whether different steps (0: ADC, 1: IIR, 2: DDS) are
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# currently active (exposed for simulation only), with each bit being
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# reset once the successor step is launched. Depending on the
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# timing details of the different steps, any number can be concurrently
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# active (e.g. ADC read from iteration n, IIR computation from iteration
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# n - 1, and DDS write from iteration n - 2).
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# Asserted once per cycle when the DDS write has been completed.
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self.done = Signal()
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self.sync += [
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If(self.dds.done,
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active[2].eq(0)
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),
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If(self.dds.start & self.dds.done,
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active[2].eq(1),
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active[1].eq(0)
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),
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If(self.iir.start & self.iir.done,
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active[1].eq(1),
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active[0].eq(0)
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),
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If(~cnt_done & self.adc.done,
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cnt.eq(cnt - 1)
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),
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If(self.adc.start & self.adc.done,
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active[0].eq(1),
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cnt.eq(t_restart - 1)
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)
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]
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self.comb += [
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cnt_done.eq(cnt == 0),
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self.adc.start.eq(self.start & cnt_done),
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self.iir.start.eq(active[0] & self.adc.done),
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self.dds.start.eq(active[1] &
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(self.iir.shifting | self.iir.done)),
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self.done.eq(self.dds.done),
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]
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