mirror of https://github.com/m-labs/artiq.git
354 lines
11 KiB
Python
354 lines
11 KiB
Python
# Copyright 2013-2017 Robert Jordens <jordens@gmail.com>
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#
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# pdq is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# pdq is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with pdq. If not, see <http://www.gnu.org/licenses/>.
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from collections import namedtuple
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from operator import add
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from migen import *
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from misoc.interconnect.stream import Endpoint
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from misoc.interconnect.csr import *
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from misoc.cores.cordic import Cordic
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from artiq.gateware.rtio import rtlink
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class DacInterface(Module, AutoCSR):
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def __init__(self, pads):
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bit_width = len(pads[0].data)
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self.data = [[Signal(bit_width) for _ in range(2)] for _ in range(8)]
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self.ddr_clk_phase_shift = CSR()
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self.ddr_clk_phase_shift_done = CSRStatus(reset=1)
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mmcm_ps_fb = Signal()
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mmcm_ps_output = Signal()
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mmcm_ps_psdone = Signal()
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ddr_clk = Signal()
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# Generate DAC DDR CLK
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# 125MHz to 125MHz with controllable phase shift,
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# VCO @ 1000MHz.
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# Phase is shifted by 45 degree by default
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self.specials += \
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=ClockSignal(),
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i_RST=ResetSignal(),
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i_CLKINSEL=1,
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p_CLKFBOUT_MULT_F=8.0,
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p_CLKOUT0_DIVIDE_F=8.0,
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p_DIVCLK_DIVIDE=1,
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p_CLKOUT0_PHASE=45.0,
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o_CLKFBOUT=mmcm_ps_fb, i_CLKFBIN=mmcm_ps_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_ps_output,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.ddr_clk_phase_shift.re,
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i_PSINCDEC=self.ddr_clk_phase_shift.r,
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o_PSDONE=mmcm_ps_psdone,
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)
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self.sync += [
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If(self.ddr_clk_phase_shift.re, self.ddr_clk_phase_shift_done.status.eq(0)),
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If(mmcm_ps_psdone, self.ddr_clk_phase_shift_done.status.eq(1))
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]
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# din.clk pads locate at multiple clock regions/IO banks
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self.specials += [
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Instance("BUFG", i_I=mmcm_ps_output, o_O=ddr_clk),
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]
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for i, din in enumerate(pads):
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self.specials += Instance("ODDR",
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i_C=ddr_clk,
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i_CE=1,
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i_D1=1,
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i_D2=0,
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o_Q=din.clk,
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p_DDR_CLK_EDGE="SAME_EDGE")
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self.specials += [
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Instance("ODDR",
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i_C=ClockSignal(),
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i_CE=1,
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i_D1=self.data[i][0][bit], # DDR CLK Rising Edge
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i_D2=self.data[i][1][bit], # DDR CLK Falling Edge
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o_Q=din.data[bit],
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p_DDR_CLK_EDGE="SAME_EDGE")
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for bit in range(bit_width)]
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class Dac(Module):
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"""Output module.
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Holds the two output line executors.
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Attributes:
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data (Signal[16]): Output value to be send to the DAC.
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clear (Signal): Clear accumulated phase offset when loading a new
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waveform. Input.
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gain (Signal[16]): Output value gain. The gain signal represents the
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decimal part os the gain in 2's complement.
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offset (Signal[16]): Output value offset.
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i (Endpoint[]): Coefficients of the output lines.
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"""
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def __init__(self):
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self.clear = Signal()
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self.data = Signal(16)
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self.gain = Signal(16)
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self.offset = Signal(16)
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###
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subs = [
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Volt(),
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Dds(self.clear),
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]
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# Infer signed multiplication
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data_raw = Signal((14, True))
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data_buf = Signal(14)
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self.sync.rio += [
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data_raw.eq(reduce(add, [sub.data for sub in subs])),
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# Extra buffer for better DSP timing
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data_buf.eq(((data_raw * Cat(self.gain, ~self.gain[-1])) + (self.offset << 16))[16:]),
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self.data.eq(data_buf),
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]
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self.i = [ sub.i for sub in subs ]
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self.submodules += subs
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class Volt(Module):
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"""DC bias spline interpolator.
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The line data is interpreted as a concatenation of:
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* 16 bit amplitude offset
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* 32 bit amplitude first order derivative
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* 48 bit amplitude second order derivative
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* 48 bit amplitude third order derivative
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Attributes:
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data (Signal[16]): Output data from this spline.
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i (Endpoint): Coefficients of the DC bias spline, along with its
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latency compensation.
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"""
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def __init__(self):
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self.data = Signal(16)
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self.i = Endpoint([("data", 144)])
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self.i.latency = 17
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###
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v = [Signal(48) for i in range(4)] # amp, damp, ddamp, dddamp
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# Increase latency of stb by 17 cycles to compensate CORDIC latency
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stb_r = [ Signal() for _ in range(17) ]
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self.sync.rio += [
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stb_r[0].eq(self.i.stb),
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]
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for idx in range(16):
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self.sync.rio += stb_r[idx+1].eq(stb_r[idx])
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self.sync.rio += [
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v[0].eq(v[0] + v[1]),
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v[1].eq(v[1] + v[2]),
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v[2].eq(v[2] + v[3]),
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If(stb_r[16],
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v[0].eq(0),
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v[1].eq(0),
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Cat(v[0][32:], v[1][16:], v[2], v[3]).eq(self.i.payload.raw_bits()),
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)
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]
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self.comb += self.data.eq(v[0][32:])
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class Dds(Module):
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"""DDS spline interpolator.
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The line data is interpreted as:
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* 16 bit amplitude offset
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* 32 bit amplitude first order derivative
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* 48 bit amplitude second order derivative
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* 48 bit amplitude third order derivative
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* 16 bit phase offset
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* 32 bit frequency word
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* 32 bit chirp
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Args:
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line (Record[line_layout]): Next line to be executed. Input.
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clear (Signal): Clear accumulated phase offset when loading a new
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waveform. Input.
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Attributes:
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data (Signal[16]): Output data from this spline.
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i (Endpoint): Coefficients of the DDS spline, along with its latency
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compensation.
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"""
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def __init__(self, clear):
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self.data = Signal(16)
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self.i = Endpoint([("data", 224)])
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###
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self.submodules.cordic = Cordic(width=16, eval_mode="pipelined",
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guard=None)
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za = Signal(32)
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z = [Signal(32) for i in range(3)] # phase, dphase, ddphase
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x = [Signal(48) for i in range(4)] # amp, damp, ddamp, dddamp
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self.comb += [
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self.cordic.xi.eq(x[0][32:]),
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self.cordic.yi.eq(0),
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self.cordic.zi.eq(za[16:] + z[0][16:]),
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self.data.eq(self.cordic.xo),
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]
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self.sync.rio += [
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za.eq(za + z[1]),
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x[0].eq(x[0] + x[1]),
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x[1].eq(x[1] + x[2]),
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x[2].eq(x[2] + x[3]),
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z[1].eq(z[1] + z[2]),
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If(self.i.stb,
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x[0].eq(0),
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x[1].eq(0),
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Cat(x[0][32:], x[1][16:], x[2], x[3], z[0][16:], z[1], z[2]
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).eq(self.i.payload.raw_bits()),
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If(clear,
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za.eq(0),
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)
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)
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]
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class Config(Module):
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def __init__(self):
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self.clr = Signal(16, reset=0xFFFF)
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self.gain = [ Signal(16) for _ in range(16) ]
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self.offset = [ Signal(16) for _ in range(16) ]
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reg_file = Array(self.gain + self.offset + [self.clr])
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self.i = Endpoint([
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("data", 16),
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("addr", 7),
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])
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self.o = Endpoint([
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("data", 16),
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])
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# This introduces 1 extra latency to everything in config
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# See the latency/delay attributes in Volt & DDS Endpoints/rtlinks
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#
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# Gain & offsets are intended for initial calibration only, latency
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# is NOT adjusted to match outputs to the DAC interface
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#
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# Interface address bits mapping:
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# 6: Read bit. Assert to read, deassert to write.
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# 5: Clear bit. Assert to write clr. clr is write-only.
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# 4: Gain/Offset. (De)Assert to access (Gain)Offset registers.
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# 0-3: Channel selection for the Gain & Offset registers.
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#
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# Reading Gain / Offset register generates an RTIOInput event
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self.sync.rio += [
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self.o.stb.eq(0),
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If(self.i.stb,
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If(~self.i.addr[6],
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reg_file[self.i.addr[:6]].eq(self.i.data),
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).Else(
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# clr register is unreadable, as an optimization
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self.o.data.eq(reg_file[self.i.addr[:5]]),
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self.o.stb.eq(1),
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)
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),
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]
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Phy = namedtuple("Phy", "rtlink probes overrides")
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class Shuttler(Module, AutoCSR):
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"""Shuttler module.
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Used both in functional simulation and final gateware.
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Holds the DACs and the configuration register. The DAC and Config are
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collected and adapted into RTIO interface.
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Attributes:
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phys (list): List of Endpoints.
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"""
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def __init__(self, pads):
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NUM_OF_DACS = 16
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self.submodules.dac_interface = DacInterface(pads)
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self.phys = []
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self.submodules.cfg = Config()
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cfg_rtl_iface = rtlink.Interface(
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rtlink.OInterface(
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data_width=len(self.cfg.i.data),
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address_width=len(self.cfg.i.addr),
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enable_replace=False,
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),
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rtlink.IInterface(
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data_width=len(self.cfg.o.data),
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),
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)
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self.comb += [
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self.cfg.i.stb.eq(cfg_rtl_iface.o.stb),
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self.cfg.i.addr.eq(cfg_rtl_iface.o.address),
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self.cfg.i.data.eq(cfg_rtl_iface.o.data),
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cfg_rtl_iface.i.stb.eq(self.cfg.o.stb),
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cfg_rtl_iface.i.data.eq(self.cfg.o.data),
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]
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self.phys.append(Phy(cfg_rtl_iface, [], []))
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trigger_iface = rtlink.Interface(rtlink.OInterface(
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data_width=NUM_OF_DACS,
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enable_replace=False))
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self.phys.append(Phy(trigger_iface, [], []))
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for idx in range(NUM_OF_DACS):
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dac = Dac()
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self.comb += [
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dac.clear.eq(self.cfg.clr[idx]),
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dac.gain.eq(self.cfg.gain[idx]),
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dac.offset.eq(self.cfg.offset[idx]),
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self.dac_interface.data[idx // 2][idx % 2].eq(dac.data)
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]
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for i in dac.i:
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delay = getattr(i, "latency", 0)
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rtl_iface = rtlink.Interface(rtlink.OInterface(
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data_width=16, address_width=4, delay=delay))
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array = Array(i.data[wi: wi+16] for wi in range(0, len(i.data), 16))
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self.sync.rio += [
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i.stb.eq(trigger_iface.o.data[idx] & trigger_iface.o.stb),
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If(rtl_iface.o.stb,
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array[rtl_iface.o.address].eq(rtl_iface.o.data),
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),
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]
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self.phys.append(Phy(rtl_iface, [], []))
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self.submodules += dac
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