mirror of https://github.com/m-labs/artiq.git
109 lines
4.8 KiB
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109 lines
4.8 KiB
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ARTIQ Phaser
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============
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This ARTIQ branch contains a proof-of-concept design of a GHz-datarate multichannel direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
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In later developments this proof-of-concept can be expanded to provide a two-tone output with spline modulation and multi-DAC synchronization.
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Ultimately it will be the basis for the ARTIQ Sayma project. See https://github.com/m-labs/sayma and https://github.com/m-labs/artiq-hardware
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The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-jitter 2 GHz reference clock.
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Features:
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* 4 channels
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* 500 MHz data rate per channel (KC705 limitation)
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* 4x interpolation to 2 GHz DAC sample rate
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* Real-time control over amplitude, frequency, phase through ARTIQ RTIO
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channels
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel
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support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured, e.g. to support 2 channels at 1 GHz datarate or to support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).
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This work was supported by the Army Research Lab.
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The additions and modifications to ARTIQ that were implemented for this project are:
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser
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* The CORDIC core has been reused from the PDQ2 gateware
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https://github.com/m-labs/pdq2
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* The Migen/MiSoC JESD204B core: https://github.com/m-labs/jesd204b
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Installation
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------------
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These installation instructions are a short form of those in the ARTIQ manual.
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Please refer to the manual for more details:
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https://m-labs.hk/artiq/manual-release-2/index.html
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* Set up a new conda environment and activate it.
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* Checkout the ARTIQ phaser branch: ::
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git clone --recursive -b phaser https://github.com/m-labs/artiq.git
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* Install the standard ARTIQ runtime/install dependencies.
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See ``conda/artiq/meta.yaml`` for a list.
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They are all packaged as conda packages in ``m-labs/main``.
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* Install the standard ARTIQ build dependencies.
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They are all available as conda packages in m-labs/main at least for linux-64:
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- migen 0.4
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- misoc 0.3
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- llvm-or1k
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- rust-core-or1k
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- cargo
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- binutils-or1k-linux >=2.27
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* Vivado
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Follow the ARTIQ manual's chapter on installing.
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Setup
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-----
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* Setup the KC705 (VADJ, jumpers, etc.) observing the ARTIQ manual.
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* On the AD9154-FMC-EBZ put jumpers:
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- on XP1, between pin 5 and 6 (will keep the PIC in reset)
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- on JP3 (will force output enable on FXLA108)
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual): ::
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python -m artiq.gateware.targets.kc705 -H phaser --toolchain vivado
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* Run the following OpenOCD commands to flash the ARTIQ transmitter design: ::
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init
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jtagspi_init 0 bscan_spi_xc7k325t.bit
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jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000
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jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000
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jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000
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xc7_program xc7.tap
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exit
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The proxy bitstream ``bscan_spi_xc7k325t.bit`` can be found at https://github.com/jordens/bscan_spi_bitstreams or in any ARTIQ conda package for the KC705. See the source code of ``artiq_flash.py`` from ARTIQ for more details.
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* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
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If the board was running stock ARTIQ before, the settings will be kept.
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* A 2 GHz of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1.
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The external RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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* The ``startup_clock`` needs to be set to internal (``i``) for bootstrapping the clock distribution tree.
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* Compile and flash the startup kernel in ``artiq/examples/phaser/startup_kernel.py``.
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Usage
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-----
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* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``.
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* After each boot, run the ``dac_setup.py`` experiment to establish and align the data link (``artiq_run repository/dac_setup.py``).
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* run ``artiq_run repository/sawg.py`` for an example that sets up amplitudes, frequencies,
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and phases on all four DDS channels.
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* Implement your own experiments using the SAWG channels.
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* Verify clock stability between the 2 GHz reference clock and the DAC outputs.
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* Verify phase alignment between the DAC channels.
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* Changes to the AD9154 configuration can also be performed at runtime in experiments.
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See the example ``startup_kernel.py``.
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This can e.g. be used to enable and evaluate mix mode without having to change any other code (bitstream/bios/runtime/startup_kernel).
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