mirror of https://github.com/m-labs/artiq.git
58 lines
2.1 KiB
Python
58 lines
2.1 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, BlindTransfer
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.cdc import CrossDomainRequest
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class RTController(Module, AutoCSR):
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def __init__(self, rt_packet):
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self.reset = CSRStorage()
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self.set_time = CSR()
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self.protocol_error = CSR(4)
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self.command_missed_cmd = CSRStatus(2)
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self.command_missed_chan_sel = CSRStatus(24)
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self.buffer_space_timeout_dest = CSRStatus(8)
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self.sync += rt_packet.reset.eq(self.reset.storage)
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set_time_stb = Signal()
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self.sync += [
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If(rt_packet.set_time_stb, set_time_stb.eq(0)),
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If(self.set_time.re, set_time_stb.eq(1))
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]
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self.comb += self.set_time.w.eq(set_time_stb)
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errors = [
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(rt_packet.err_unknown_packet_type, "rtio_rx", None, None),
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(rt_packet.err_packet_truncated, "rtio_rx", None, None),
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(rt_packet.err_command_missed, "sys",
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Cat(rt_packet.command_missed_cmd, rt_packet.command_missed_chan_sel),
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Cat(self.command_missed_cmd.status, self.command_missed_chan_sel.status)),
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(rt_packet.err_buffer_space_timeout, "sys",
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rt_packet.buffer_space_destination, self.buffer_space_timeout_dest.status)
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]
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for n, (err_i, err_cd, din, dout) in enumerate(errors):
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if din is not None:
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data_width = len(din)
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else:
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data_width = 0
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xfer = BlindTransfer(err_cd, "sys", data_width=data_width)
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self.submodules += xfer
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self.comb += xfer.i.eq(err_i)
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err_pending = Signal()
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self.sync += [
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If(self.protocol_error.re & self.protocol_error.r[n], err_pending.eq(0)),
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If(xfer.o, err_pending.eq(1))
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]
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self.comb += self.protocol_error.w[n].eq(err_pending)
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if din is not None:
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self.comb += xfer.data_i.eq(din)
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self.sync += If(xfer.o & ~err_pending, dout.eq(xfer.data_o))
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