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272 lines
8.9 KiB
TeX
272 lines
8.9 KiB
TeX
\documentclass[final,presentation,compress]{beamer}
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\usepackage[mathcal]{euler}
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\usepackage{amsmath, amssymb, amsopn} %amssymb,amstext
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\usepackage[cm-default]{fontspec}
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\usepackage{xltxtra}
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\usepackage[english]{babel}
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\usepackage{multicol}
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\usepackage{multimedia}
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\usepackage{tikz}
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\usetikzlibrary{arrows,shapes,snakes,positioning,backgrounds,decorations,graphs}
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\definecolor{ethblue}{rgb}{0, 0.2, 0.3568}
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\usepackage{minted}
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\mode<presentation>
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{
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\useoutertheme{default} % simplistic
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\setbeamertemplate{headline}[default] % kill the headline
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\setbeamertemplate{navigation symbols}{} % no navigaton stuff in lr corner
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\useinnertheme{circles}
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\setbeamercolor*{palette primary}{use=structure,fg=white,bg=ethblue!70}
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\setbeamercolor*{palette secondary}{use=structure,fg=white,bg=ethblue!80}
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\setbeamercolor*{palette tertiary}{use=structure,fg=white,bg=ethblue!90}
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\setbeamercolor*{palette quaternary}{use=structure,fg=white,bg=ethblue!100}
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\setbeamercolor*{structure}{fg=ethblue!70}
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\hypersetup{
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}
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\setbeamercovered{invisible}
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}
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\graphicspath{{fig//}}
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\title{Real-time experiment control for quantum physics}
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\author[Robert~Jördens]{{\bf Robert~Jördens}}
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\institute[]{
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Ion Storage Group, Time and Frequency, NIST, Boulder, CO \\
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\url{rjordens@nist.gov}%
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}
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\begin{document}
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\begin{frame}[plain]
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\titlepage
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\tikz[overlay,remember picture]\node[anchor=south,above=-.5cm] at (current page.south)
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{\includegraphics[width=\paperwidth]{flatirons_winter_wikipedia}};
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\tikz[overlay,remember picture]\node[anchor=south east, fill=white,
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inner sep=.3mm] at (current page.south east) {%
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\tiny Jesse Varner, AzaToth, CC-BY-SA};
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\end{frame}
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\begin{frame}
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\includegraphics[width=\columnwidth]{jost_trap-3}
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\end{frame}
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\begin{frame}
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\frametitle{Quantum gate sequences}
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\includegraphics[width=\columnwidth]{gate_sequence}
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\end{frame}
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\begin{frame}
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\begin{tikzpicture}[box/.style={rectangle,fill=white}]
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\node[inner sep=0] {\includegraphics[width=\columnwidth]{lab}};\pause
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%\draw[help lines,white] (-4, -3) grid (4, 3);
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\node[box] at (-4, -2) {FPGA};
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\node[box] at (3.5, 0) {ion trap};
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\node[box] at (-3, 3) {$\sim$10 attenuators};
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\node[box] at (2, 2) {$\sim$50 DAC};
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\node[box] at (-4, 0) {$\sim$20 DDS};
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\node[box] at (-2, 1) {$\sim$50 GPIO};
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\node[box] at (.5, 0) {$\sim$10 motors};
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\node[box] at (2, -2) {$\sim$10 power supplies};
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\node[box] at (4, -3) {$\sim$10 lasers};
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\end{tikzpicture}
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\end{frame}
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\begin{frame}
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\frametitle{Physicists are not programmers:}
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\footnotesize
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\begin{center}
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\only<1>{\includegraphics[width=\columnwidth]{labview}\\
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LabVIEW: a ``visual programming language'' (a.k.a. ``high viscosity language'')}
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\only<2>{\includegraphics[width=\columnwidth]{expwiz_matrix}\\
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Rigid time-versus-channel matrix: inflexible (loops, conditionals?)}
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\only<3>{\includegraphics[width=\columnwidth]{control_buttons}\\
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Hard-coded components: not generic and opaque implementation}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Enter ARTIQ}
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\alert{A}dvanced \alert{R}eal-\alert{T}ime \alert{I}nfrastructure for \alert{Q}uantum physics
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\footnotesize
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\begin{itemize}
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\item High performance --- nanosecond resolution, hundreds of ns latency
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\item Expressive --- describe algorithms with few lines of code
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\item Portable --- treat hardware, especially FPGA boards, as commodity
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\item Modular --- separate components as much as possible
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\item Flexible --- hard-code as little as possible
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\end{itemize}
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\end{frame}
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\begin{frame}[fragile]
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\frametitle{Define a simple timing language}
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\footnotesize
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\begin{minted}[frame=leftline]{python}
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trigger.sync() # wait for trigger input
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start = now() # capture trigger time
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for i in range(3):
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delay(5*us)
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dds.pulse(900*MHz, 7*us) # first pulse 5 µs after trigger
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at(start + 1*ms) # re-reference time-line
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dds.pulse(200*MHz, 11*us) # exactly 1 ms after trigger
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\end{minted}
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\begin{itemize}
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\item Written in a subset of Python
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\item Executed on a CPU embedded on a FPGA (the \emph{core device})
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\item \verb!now(), at(), delay()! describe time-line of an experiment
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\item Exact time is kept in an internal variable
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\item That variable only loosely tracks the execution time of CPU instructions
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\item The value of that variable is exchanged with the RTIO fabric that
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does precise timing
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\end{itemize}
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\end{frame}
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\begin{frame}[fragile]
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\frametitle{Convenient syntax additions}
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\footnotesize
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\begin{minted}[frame=leftline]{python}
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with sequential:
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with parallel:
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a.pulse(100*MHz, 10*us)
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b.pulse(200*MHz, 20*us)
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with parallel:
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c.pulse(300*MHz, 30*us)
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d.pulse(400*MHz, 20*us)
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\end{minted}
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\begin{itemize}
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\item Experiments are inherently parallel:
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simultaneous laser pulses, parallel cooling of ions in different trap zones
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\item \verb!parallel! and \verb!sequential! contexts with arbitrary nesting
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\item \verb!a! and \verb!b! pulses both start at the same time
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\item \verb!c! and \verb!d! pulses both start when \verb!a! and \verb!b! are both done
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(after 20\,µs)
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\item Implemented by inlining, loop-unrolling, and interleaving
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\end{itemize}
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\end{frame}
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\begin{frame}[fragile]
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\frametitle{Physical quantities, hardware granularity}
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\footnotesize
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\begin{minted}[frame=leftline]{python}
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n = 1000
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dt = 1.2345*ns
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f = 345*MHz
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dds.on(f, phase=0) # must round to integer tuning word
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for i in range(n):
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delay(dt) # must round to native cycles
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dt_raw = time_to_cycles(dt) # integer number of cycles
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f_raw = dds.frequency_to_ftw(f) # integer frequency tuning word
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# determine correct phase despite accumulation of rounding errors
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phi = n*cycles_to_time(dt_raw)*dds.ftw_to_frequency(f_raw)
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\end{minted}
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\begin{itemize}
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\item Need well defined conversion and rounding of physical quantities
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(time, frequency, phase, etc.) to hardware granularity and back
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\item Complicated because of calibration, offsets, cable delays,
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non-linearities
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\item No generic way to do it automatically and correctly
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\item $\rightarrow$ need to do it explicitly where it matters
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\end{itemize}
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\end{frame}
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\begin{frame}[fragile]
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\frametitle{Invite organizing experiment components and code reuse}
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\footnotesize
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\begin{minted}[frame=leftline]{python}
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class Experiment:
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def build(self):
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self.ion1 = Ion(...)
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self.ion2 = Ion(...)
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self.transporter = Transporter(...)
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@kernel
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def run(self):
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with parallel:
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self.ion1.cool(duration=10*us)
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self.ion2.cool(frequency=...)
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self.transporter.move(speed=...)
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delay(100*ms)
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self.ion1.detect(duration=...)
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\end{minted}
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\end{frame}
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\begin{frame}[fragile]
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\frametitle{RPC to handle distributed non-RT hardware}
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\footnotesize
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\begin{minted}[frame=leftline]{python}
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class Experiment:
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def prepare(self): # runs on the host
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self.motor.move_to(20*mm) # slow RS232 motor controller
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@kernel
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def run(self): # runs on the RT core device
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self.prepare() # converted into an RPC
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\end{minted}
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\begin{itemize}
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\item When a kernel function calls a non-kernel function, it generates a RPC
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\item The callee is executed on the host
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\item Mechanism to report results and control slow devices
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\item The kernel must have a loose real-time constraint (a long \verb!delay!)
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or means of re-synchronization to cover communication, host, and device delays
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{Kernel deployment to the core device}
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\footnotesize
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\begin{itemize}
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\item RPC and exception mappings are generated
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\item Constants and small kernels are inlined
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\item Small loops are unrolled
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\item Statements in parallel blocks are interleaved
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\item Time is converted to RTIO clock cycles
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\item The Python AST is converted to LLVM IR
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\item The LLVM IR is compiled to OpenRISC machine code
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\item The OpenRISC binary is sent to the core device
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\item The runtime in the core device links and runs the kernel
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\item The kernel calls the runtime for communication (RPC) and interfacing
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with core device peripherals (RTIO, DDS)
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\end{itemize}
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\end{frame}
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\begin{frame}
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\begin{center}
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\url{https://github.com/m-labs/artiq}
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\end{center}
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\footnotesize
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\begin{itemize}
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\item Fully open-source, BSD licensed
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\item Ported and running on two different FPGA boards
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\item Design applicable beyond ion trapping (superconducting qubits,
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neutral atoms...)
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\item Fastest open-source DDR3 SODIMM controller as a sub-project: 64\,Gbps
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\item Interfacing with lab hardware
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\item Hardware-in-the-loop unittests
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\item Self-contained simulator
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\item Currently $\sim$1\,µs latency and $\sim$1\,MHz event rate
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\item DMA should improve that dramatically
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\end{itemize}
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\end{frame}
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\end{document}
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% vim:ts=2:sw=2:et:ai
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