mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-05 09:46:36 +08:00
488 lines
17 KiB
Python
488 lines
17 KiB
Python
from itertools import product
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from migen import *
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from migen.genlib.fsm import FSM, NextState
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from misoc.interconnect import wishbone
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class SPIClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.bias = Signal() # bias this clock phase to longer times
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self.edge = Signal()
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self.clk = Signal(reset=1)
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cnt = Signal.like(self.load)
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bias = Signal()
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zero = Signal()
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self.comb += [
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zero.eq(cnt == 0),
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self.edge.eq(zero & ~bias),
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]
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self.sync += [
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If(zero,
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bias.eq(0),
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).Else(
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cnt.eq(cnt - 1),
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),
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If(self.edge,
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cnt.eq(self.load[1:]),
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bias.eq(self.load[0] & (self.clk ^ self.bias)),
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self.clk.eq(~self.clk),
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)
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]
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class SPIRegister(Module):
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def __init__(self, width):
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self.data = Signal(width)
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self.o = Signal()
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self.i = Signal()
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self.lsb = Signal()
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self.shift = Signal()
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self.sample = Signal()
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self.comb += [
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self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
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]
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self.sync += [
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If(self.shift,
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If(self.lsb,
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self.data[:-1].eq(self.data[1:]),
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).Else(
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self.data[1:].eq(self.data[:-1]),
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)
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),
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If(self.sample,
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If(self.lsb,
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self.data[-1].eq(self.i),
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).Else(
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self.data[0].eq(self.i),
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)
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)
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]
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class SPIBitCounter(Module):
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def __init__(self, width):
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self.n_read = Signal(width)
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self.n_write = Signal(width)
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self.read = Signal()
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self.write = Signal()
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self.done = Signal()
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self.comb += [
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self.write.eq(self.n_write != 0),
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self.read.eq(self.n_read != 0),
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self.done.eq(~(self.write | self.read)),
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]
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self.sync += [
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If(self.write,
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self.n_write.eq(self.n_write - 1),
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).Elif(self.read,
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self.n_read.eq(self.n_read - 1),
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)
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]
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class SPIMachine(Module):
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def __init__(self, data_width, clock_width, bits_width):
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ce = CEInserter()
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self.submodules.cg = ce(SPIClockGen(clock_width))
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self.submodules.reg = ce(SPIRegister(data_width))
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self.submodules.bits = ce(SPIBitCounter(bits_width))
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self.div_write = Signal.like(self.cg.load)
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self.div_read = Signal.like(self.cg.load)
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self.clk_phase = Signal()
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self.start = Signal()
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self.cs = Signal()
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self.oe = Signal()
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self.done = Signal()
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# # #
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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If(self.clk_phase,
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NextState("WAIT"),
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).Else(
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NextState("SETUP"),
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)
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)
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)
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fsm.act("SETUP",
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self.reg.sample.eq(1),
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NextState("HOLD"),
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)
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fsm.act("HOLD",
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If(self.bits.done & ~self.start,
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If(self.clk_phase,
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NextState("IDLE"),
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).Else(
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NextState("WAIT"),
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)
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).Else(
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self.reg.shift.eq(1),
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NextState("SETUP"),
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)
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)
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fsm.act("WAIT",
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If(self.bits.done,
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NextState("IDLE"),
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).Else(
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NextState("SETUP"),
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)
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)
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write0 = Signal()
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self.sync += [
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If(self.cg.edge & self.reg.shift,
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write0.eq(self.bits.write),
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)
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]
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self.comb += [
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self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
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If(self.bits.write | ~self.bits.read,
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self.cg.load.eq(self.div_write),
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).Else(
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self.cg.load.eq(self.div_read),
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),
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self.cg.bias.eq(self.clk_phase),
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fsm.ce.eq(self.cg.edge),
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self.cs.eq(~fsm.ongoing("IDLE")),
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self.reg.ce.eq(self.cg.edge),
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self.bits.ce.eq(self.cg.edge & self.reg.sample),
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self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
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self.oe.eq(write0 | self.bits.write),
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]
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class SPIMaster(Module):
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"""SPI Master.
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Notes:
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* M = 32 is the data width (width of the data register,
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maximum write bits, maximum read bits)
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* Every transfer consists of a write_length 0-M bit write followed
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by a read_length 0-M bit read.
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* cs_n is asserted at the beginning and deasserted at the end of the
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transfer if there is no other transfer pending.
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* cs_n handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "cs_n all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if miso is either not connected between slaves, or open collector,
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or correctly multiplexed externally.
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* If config.cs_polarity == 0 (cs active low, the default),
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"cs_n all deasserted" means "all cs_n bits high".
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* cs is not mandatory in pads. Framing and chip selection can also
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be handled independently through other means.
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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must to be set when reading data is desired.
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* For 4-wire SPI only the sum of read_length and write_length matters.
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The behavior is the same no matter how the total transfer length is
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divided between the two. For 3-wire SPI, the direction of mosi/miso
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is switched from output to input after write_len cycles, at the
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"shift_out" clk edge corresponding to bit write_length + 1 of the
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transfer.
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* The first bit output on mosi is always the MSB/LSB (depending on
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config.lsb_first) of the data register, independent of
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xfer.write_len. The last bit input from miso always ends up in
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the LSB/MSB (respectively) of the data register, independent of
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read_len.
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* Data output on mosi in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the data register outside the least/most (depending
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on config.lsb_first) significant read_length bits is what is
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seen on miso during the write cycles.
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* The SPI data register is double-buffered: Once a transfer has
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started, new write data can be written, queuing a new transfer.
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Transfers submitted this way are chained and executed without
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deasserting cs. Once a transfer completes, the previous transfer's
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read data is available in the data register.
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* Writes to the config register take effect immediately. Writes to xfer
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and data are synchronized to the start of a transfer.
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* A wishbone data register write is ack-ed when the transfer has
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been written to the intermediate buffer. It will be started when
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there are no other transactions being executed, either starting
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a new SPI transfer of chained to an in-flight transfer.
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Writes take two cycles unless the write is to the data register
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and another chained transfer is pending and the transfer being
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executed is not complete. Reads always finish in two cycles.
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Transaction Sequence:
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* If desired, write the config register to set up the core.
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* If desired, write the xfer register to change lengths and cs_n.
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* Write the data register (also for zero-length writes),
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writing triggers the transfer and when the transfer is accepted to
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the inermediate buffer, the write is ack-ed.
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* If desired, read the data register corresponding to the last
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completed transfer.
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* If desired, change xfer register for the next transfer.
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* If desired, write data queuing the next (possibly chained) transfer.
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Register address and bit map:
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config (address 2):
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1 offline: all pins high-z (reset=1)
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1 active: cs/transfer active (read-only)
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1 pending: transfer pending in intermediate buffer (read-only)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level of clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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(clk_polarity, clk_phase) == (CPOL, CPHA) in Freescale language.
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(0, 0): idle low, output on falling, input on rising
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(0, 1): idle low, output on rising, input on falling
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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There is never a clk edge during a cs edge.
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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8 undefined
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8 div_write: counter load value to divide this module's clock
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to generate the SPI write clk (reset=0)
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f_clk/f_spi_write == div_write + 2
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8 div_read: ditto for the read clock
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xfer (address 1):
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16 cs: active high bit mask of chip selects to assert (reset=0)
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6 write_len: 0-M bits (reset=0)
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2 undefined
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6 read_len: 0-M bits (reset=0)
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2 undefined
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data (address 0):
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M write/read data (reset=0)
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"""
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def __init__(self, pads, bus=None):
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if bus is None:
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bus = wishbone.Interface(data_width=32)
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self.bus = bus
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###
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# Wishbone
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config = Record([
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("offline", 1),
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("active", 1),
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("pending", 1),
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("cs_polarity", 1),
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("clk_polarity", 1),
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("clk_phase", 1),
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("lsb_first", 1),
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("half_duplex", 1),
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("padding", 8),
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("div_write", 8),
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("div_read", 8),
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])
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config.offline.reset = 1
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assert len(config) <= len(bus.dat_w)
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xfer = Record([
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("cs", 16),
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("write_length", 6),
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("padding0", 2),
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("read_length", 6),
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("padding1", 2),
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])
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assert len(xfer) <= len(bus.dat_w)
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self.submodules.spi = spi = SPIMachine(
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data_width=len(bus.dat_w),
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clock_width=len(config.div_read),
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bits_width=len(xfer.read_length))
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pending = Signal()
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cs = Signal.like(xfer.cs)
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data_read = Signal.like(spi.reg.data)
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data_write = Signal.like(spi.reg.data)
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self.comb += [
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bus.dat_r.eq(
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Array([data_read, xfer.raw_bits(), config.raw_bits()
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])[bus.adr]),
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spi.start.eq(pending & (~spi.cs | spi.done)),
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spi.clk_phase.eq(config.clk_phase),
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spi.reg.lsb.eq(config.lsb_first),
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spi.div_write.eq(config.div_write),
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spi.div_read.eq(config.div_read),
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]
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self.sync += [
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If(spi.done,
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data_read.eq(spi.reg.data),
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),
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If(spi.start,
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cs.eq(xfer.cs),
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spi.bits.n_write.eq(xfer.write_length),
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spi.bits.n_read.eq(xfer.read_length),
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spi.reg.data.eq(data_write),
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pending.eq(0),
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),
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# wb.ack a transaction if any of the following:
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# a) reading,
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# b) writing to non-data register
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# c) writing to data register and no pending transfer
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# d) writing to data register and pending and swapping buffers
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bus.ack.eq(bus.cyc & bus.stb &
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(~bus.we | (bus.adr != 0) | ~pending | spi.done)),
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If(bus.ack,
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bus.ack.eq(0),
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If(bus.we,
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Array([data_write, xfer.raw_bits(), config.raw_bits()
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])[bus.adr].eq(bus.dat_w),
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If(bus.adr == 0, # data register
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pending.eq(1),
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),
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),
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),
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config.active.eq(spi.cs),
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config.pending.eq(pending),
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]
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# I/O
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if hasattr(pads, "cs_n"):
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cs_n_t = TSTriple(len(pads.cs_n))
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self.specials += cs_n_t.get_tristate(pads.cs_n)
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self.comb += [
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cs_n_t.oe.eq(~config.offline),
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cs_n_t.o.eq((cs & Replicate(spi.cs, len(cs))) ^
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Replicate(~config.cs_polarity, len(cs))),
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]
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clk_t = TSTriple()
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self.specials += clk_t.get_tristate(pads.clk)
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self.comb += [
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clk_t.oe.eq(~config.offline),
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clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
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]
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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mosi_t.oe.eq(~config.offline & spi.cs &
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(spi.oe | ~config.half_duplex)),
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mosi_t.o.eq(spi.reg.o),
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spi.reg.i.eq(Mux(config.half_duplex, mosi_t.i,
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getattr(pads, "miso", mosi_t.i))),
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]
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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(
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SPI_OFFLINE,
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SPI_ACTIVE,
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SPI_PENDING,
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SPI_CS_POLARITY,
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SPI_CLK_POLARITY,
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SPI_CLK_PHASE,
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SPI_LSB_FIRST,
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SPI_HALF_DUPLEX,
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) = (1 << i for i in range(8))
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def SPI_DIV_WRITE(i):
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return i << 16
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def SPI_DIV_READ(i):
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return i << 24
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def SPI_CS(i):
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return i << 0
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def SPI_WRITE_LENGTH(i):
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return i << 16
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def SPI_READ_LENGTH(i):
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return i << 24
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def _test_xfer(bus, cs, wlen, rlen, wdata):
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(cs) |
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SPI_WRITE_LENGTH(wlen) | SPI_READ_LENGTH(rlen))
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yield from bus.write(SPI_DATA_ADDR, wdata)
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yield
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def _test_read(bus, sync=SPI_ACTIVE | SPI_PENDING):
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while (yield from bus.read(SPI_CONFIG_ADDR)) & sync:
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pass
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return (yield from bus.read(SPI_DATA_ADDR))
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def _test_gen(bus):
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yield from bus.write(SPI_CONFIG_ADDR,
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0*SPI_CLK_PHASE | 0*SPI_LSB_FIRST |
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1*SPI_HALF_DUPLEX |
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SPI_DIV_WRITE(3) | SPI_DIV_READ(5))
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yield from _test_xfer(bus, 0b01, 4, 0, 0x90000000)
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print(hex((yield from _test_read(bus))))
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yield from _test_xfer(bus, 0b10, 0, 4, 0x90000000)
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print(hex((yield from _test_read(bus))))
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yield from _test_xfer(bus, 0b11, 4, 4, 0x81000000)
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print(hex((yield from _test_read(bus))))
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yield from _test_xfer(bus, 0b01, 8, 32, 0x87654321)
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yield from _test_xfer(bus, 0b01, 0, 32, 0x12345678)
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print(hex((yield from _test_read(bus, SPI_PENDING))))
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print(hex((yield from _test_read(bus, SPI_ACTIVE))))
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return
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for cpol, cpha, lsb, clk in product(
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(0, 1), (0, 1), (0, 1), (0, 1)):
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yield from bus.write(SPI_CONFIG_ADDR,
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cpol*SPI_CLK_POLARITY | cpha*SPI_CLK_PHASE |
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lsb*SPI_LSB_FIRST | SPI_DIV_WRITE(clk) |
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SPI_DIV_READ(clk))
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for wlen, rlen, wdata in product((0, 8, 32), (0, 8, 32),
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(0, 0xffffffff, 0xdeadbeef)):
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rdata = (yield from _test_xfer(bus, 0b1, wlen, rlen, wdata, True))
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len = (wlen + rlen) % 32
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mask = (1 << len) - 1
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if lsb:
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shift = (wlen + rlen) % 32
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else:
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shift = 0
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a = (wdata >> wshift) & wmask
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b = (rdata >> rshift) & rmask
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if a != b:
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print("ERROR", end=" ")
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print(cpol, cpha, lsb, clk, wlen, rlen,
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hex(wdata), hex(rdata), hex(a), hex(b))
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class _TestPads:
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def __init__(self):
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self.cs_n = Signal(2)
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self.clk = Signal()
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self.mosi = Signal()
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self.miso = Signal()
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class _TestTristate(Module):
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def __init__(self, t):
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oe = Signal()
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self.comb += [
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t.target.eq(t.o),
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oe.eq(t.oe),
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t.i.eq(t.o),
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]
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if __name__ == "__main__":
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from migen.fhdl.specials import Tristate
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pads = _TestPads()
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dut = SPIMaster(pads)
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dut.comb += pads.miso.eq(pads.mosi)
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# from migen.fhdl.verilog import convert
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# print(convert(dut))
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Tristate.lower = _TestTristate
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run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
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