mirror of https://github.com/m-labs/artiq.git
57 lines
2.0 KiB
Python
57 lines
2.0 KiB
Python
from migen import *
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from artiq.gateware.rtio import rtlink
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from .fastlink import SerDes, SerInterface
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class Phaser(Module):
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def __init__(self, pins, pins_n):
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self.config = rtlink.Interface(
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rtlink.OInterface(data_width=8, address_width=8,
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enable_replace=False),
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rtlink.IInterface(data_width=10))
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self.data = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=8,
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enable_replace=True))
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self.submodules.serializer = SerDes(
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n_data=8, t_clk=8, d_clk=0b00001111,
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n_frame=10, n_crc=6, poly=0x2f)
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self.submodules.intf = SerInterface(pins, pins_n)
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self.comb += [
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Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
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self.serializer.data[-1].eq(self.intf.data[-1]),
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]
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header = Record([
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("we", 1),
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("addr", 7),
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("data", 8),
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("type", 4)
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])
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n_channels = 2
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n_samples = 8
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n_bits = 14
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body = [[(Signal(n_bits), Signal(n_bits))
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for i in range(n_channels)] for j in range(n_samples)]
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assert len(Cat(header.raw_bits(), body)) == \
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len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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re_dly = Signal(3) # stage, send, respond
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self.sync.rtio += [
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header.type.eq(1), # reserved
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If(self.serializer.stb,
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header.we.eq(0),
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re_dly.eq(re_dly[1:]),
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),
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If(self.config.o.stb,
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re_dly[-1].eq(~self.config.o.address[-1]),
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header.we.eq(self.config.o.address[-1]),
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header.addr.eq(self.config.o.address),
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header.data.eq(self.config.o.data),
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),
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self.config.i.stb.eq(re_dly[0] & self.serializer.stb),
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self.config.i.data.eq(self.serializer.readback),
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]
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