mirror of https://github.com/m-labs/artiq.git
56 lines
2.0 KiB
Python
56 lines
2.0 KiB
Python
from migen import *
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from misoc.interconnect import stream
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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from artiq.gateware.serwb.packet import Packetizer, Depacketizer
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from artiq.gateware.serwb.etherbone import Etherbone
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class SERWBCore(Module):
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def __init__(self, phy, clk_freq, mode, with_scrambling=False):
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# etherbone
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self.submodules.etherbone = etherbone = Etherbone(mode)
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# packetizer / depacketizer
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depacketizer = Depacketizer(clk_freq)
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packetizer = Packetizer()
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self.submodules += depacketizer, packetizer
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# clock domain crossing
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tx_cdc = stream.AsyncFIFO([("data", 32)], 16)
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tx_cdc = ClockDomainsRenamer({"write": "sys", "read": phy.cd})(tx_cdc)
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rx_cdc = stream.AsyncFIFO([("data", 32)], 16)
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rx_cdc = ClockDomainsRenamer({"write": phy.cd, "read": "sys"})(rx_cdc)
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self.submodules += tx_cdc, rx_cdc
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# scrambling
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scrambler = ClockDomainsRenamer(phy.cd)(Scrambler(enable=with_scrambling))
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descrambler = ClockDomainsRenamer(phy.cd)(Descrambler(enable=with_scrambling))
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self.submodules += scrambler, descrambler
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# modules connection
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self.comb += [
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# core --> phy
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packetizer.source.connect(tx_cdc.sink),
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tx_cdc.source.connect(scrambler.sink),
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If(phy.init.ready,
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If(scrambler.source.stb,
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phy.serdes.tx_k.eq(scrambler.source.k),
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phy.serdes.tx_d.eq(scrambler.source.d)
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),
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scrambler.source.ack.eq(1)
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),
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# phy --> core
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descrambler.sink.stb.eq(phy.init.ready),
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descrambler.sink.k.eq(phy.serdes.rx_k),
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descrambler.sink.d.eq(phy.serdes.rx_d),
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descrambler.source.connect(rx_cdc.sink),
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rx_cdc.source.connect(depacketizer.sink),
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# etherbone <--> core
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depacketizer.source.connect(etherbone.sink),
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etherbone.source.connect(packetizer.sink)
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]
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