mirror of https://github.com/m-labs/artiq.git
580 lines
23 KiB
Python
Executable File
580 lines
23 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os
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import warnings
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from migen import *
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from misoc.cores import gpio
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect.csr import *
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from misoc.targets.sayma_amc import *
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import eem
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from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerExtFF
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class RTMUARTForward(Module):
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def __init__(self, platform):
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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class SatelliteBase(MiniSoC):
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mem_map = {
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"drtioaux": 0x14000000,
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", *, with_wrpll, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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add_identifier(self, suffix=identifier_suffix)
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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if with_wrpll:
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clock_recout_pads = platform.request("ddmtd_rec_clk")
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else:
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clock_recout_pads = None
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# Use SFP0 to connect to master (Kasli)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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drtio_data_pads = [
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platform.request("sfp", 0),
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platform.request("rtm_amc_link")
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq,
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clock_recout_pads=clock_recout_pads)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[i],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if with_wrpll:
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self.comb += [
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platform.request("filtered_clk_sel").eq(0),
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platform.request("ddmtd_main_dcxo_oe").eq(1),
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platform.request("ddmtd_helper_dcxo_oe").eq(1)
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]
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self.submodules.wrpll_sampler = DDMTDSamplerExtFF(
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platform.request("ddmtd_inputs"))
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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else:
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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def add_rtio(self, rtio_channels):
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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# JESD204 DAC Channel Group
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class JDCGSAWG(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.submodules.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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assert len(Cat(ch.o)) == len(conv)
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self.sync.jesd += conv.eq(Cat(ch.o))
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class JDCGPattern(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.sawgs = []
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ramp = Signal(4)
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self.sync.rtio += ramp.eq(ramp + 1)
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samples = [[Signal(16) for i in range(4)] for j in range(4)]
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self.comb += [
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a.eq(Cat(b)) for a, b in zip(
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self.jesd.core.sink.flatten(), samples)
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]
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# ch0: 16-step ramp with big carry toggles
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for i in range(4):
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self.comb += [
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samples[0][i][-4:].eq(ramp),
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samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800)
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]
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# ch1: 50 MHz
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from math import pi, cos
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data = [int(round(cos(i/12*2*pi)*((1 << 15) - 1)))
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for i in range(12)]
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k = Signal(2)
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self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1))
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self.comb += [
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Case(k, {
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i: [samples[1][j].eq(data[i*4 + j]) for j in range(4)]
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for i in range(3)
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})
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]
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# ch2: ch0, ch3: ch1
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self.comb += [
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Cat(samples[2]).eq(Cat(samples[0])),
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Cat(samples[3]).eq(Cat(samples[1]))
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]
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class JDCGSyncDDS(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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self.coarse_ts = Signal(32)
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self.sawgs = []
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ftw = round(2**len(self.coarse_ts)*9e6/150e6)
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parallelism = 4
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mul_1 = Signal.like(self.coarse_ts)
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mul_2 = Signal.like(self.coarse_ts)
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mul_3 = Signal.like(self.coarse_ts)
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self.sync.rtio += [
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mul_1.eq(self.coarse_ts*ftw),
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mul_2.eq(mul_1),
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mul_3.eq(mul_2)
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]
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phases = [Signal.like(self.coarse_ts) for i in range(parallelism)]
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self.sync.rtio += [phases[i].eq(mul_3 + i*ftw//parallelism)
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for i in range(parallelism)]
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resolution = 10
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steps = 2**resolution
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from math import pi, cos
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data = [(2**16 + round(cos(i/steps*2*pi)*((1 << 15) - 1))) & 0xffff
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for i in range(steps)]
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samples = [Signal(16) for i in range(4)]
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for phase, sample in zip(phases, samples):
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table = Memory(16, steps, init=data)
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table_port = table.get_port(clock_domain="rtio")
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self.specials += table, table_port
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self.comb += [
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table_port.adr.eq(phase >> (len(self.coarse_ts) - resolution)),
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sample.eq(table_port.dat_r)
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]
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self.sync.rtio += [sink.eq(Cat(samples))
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for sink in self.jesd.core.sink.flatten()]
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class Satellite(SatelliteBase):
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"""
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DRTIO satellite with local DAC/SAWG channels.
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"""
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def __init__(self, jdcg_type, **kwargs):
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SatelliteBase.__init__(self, 150e6,
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identifier_suffix="." + jdcg_type,
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**kwargs)
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platform = self.platform
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self.submodules += RTMUARTForward(platform)
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# RTM bitstream upload
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slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
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self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
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slave_fpga_cfg.cclk,
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slave_fpga_cfg.din,
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slave_fpga_cfg.done,
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slave_fpga_cfg.init_b,
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slave_fpga_cfg.program_b,
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])
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self.csr_devices.append("slave_fpga_cfg")
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self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 1)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
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platform, use_rtio_clock=True)
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cls = {
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"sawg": JDCGSAWG,
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"pattern": JDCGPattern,
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"syncdds": JDCGSyncDDS
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}[jdcg_type]
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self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
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self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
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self.csr_devices.append("jesd_crg")
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self.csr_devices.append("jdcg_0")
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self.csr_devices.append("jdcg_1")
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self.config["HAS_JDCG"] = None
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self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.jdcg_0.sawgs +
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self.jdcg_1.sawgs
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for phy in sawg.phys)
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self.add_rtio(rtio_channels)
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
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if jdcg_type == "syncdds":
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self.comb += [
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self.jdcg_0.coarse_ts.eq(self.rtio_tsc.coarse_ts),
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self.jdcg_1.coarse_ts.eq(self.rtio_tsc.coarse_ts),
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]
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class SimpleSatellite(SatelliteBase):
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def __init__(self, **kwargs):
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SatelliteBase.__init__(self, **kwargs)
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platform = self.platform
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self.submodules += RTMUARTForward(platform)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 1)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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class Master(MiniSoC, AMPSoC):
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"""
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DRTIO master with 2 SFP ports plus 8 lanes on RTM.
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Use passive RTM adapter to connect to satellites.
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Due to GTH clock routing restrictions, it is not possible
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to use more RTM lanes without additional hardware.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"drtioaux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += RTMUARTForward(platform)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("sfp", 0)] +
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[platform.request("rtm_gth", i) for i in range(8)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth0 = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth0.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth0.txoutclk, gth0.rxoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth0.txoutclk, gth.rxoutclk)
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self.rtio_channels = rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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mcx_io = platform.request("mcx_io", 1)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.comb += mcx_io.direction.eq(phy.oe)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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|
|
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platform.add_extension(fmcdio_vhdci_eem.io)
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platform.add_connectors(fmcdio_vhdci_eem.connectors)
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fmcdio_dirctl = platform.request("fmcdio_dirctl")
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for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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phy = ttl_simple.Output(s)
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self.submodules += phy
|
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rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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iostandard="LVDS")
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eem.Urukul.add_std(self, 0, 1, ttl_simple.Output,
|
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iostandard="LVDS")
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eem.Zotino.add_std(self, 3, ttl_simple.Output,
|
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iostandard="LVDS")
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workaround_us_lvds_tristate(platform)
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|
|
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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|
|
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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|
|
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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|
|
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
|
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
|
rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.rtio.cri, self.rtio_dma.cri],
|
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[self.rtio_core.cri] + drtio_cri,
|
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="Sayma AMC gateware and firmware builder")
|
|
builder_args(parser)
|
|
soc_sayma_amc_args(parser)
|
|
parser.set_defaults(output_dir="artiq_sayma")
|
|
parser.add_argument("-V", "--variant", default="satellite",
|
|
help="variant: satellite/simplesatellite/master "
|
|
"(default: %(default)s)")
|
|
parser.add_argument("--rtm-csr-csv",
|
|
default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
|
|
help="CSV file listing remote CSRs on RTM (default: %(default)s)")
|
|
parser.add_argument("--jdcg-type",
|
|
default="sawg",
|
|
help="Change type of signal generator. This is used exclusively for "
|
|
"development and debugging.")
|
|
parser.add_argument("--with-wrpll", default=False, action="store_true")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
if variant == "satellite":
|
|
soc = Satellite(jdcg_type=args.jdcg_type, with_wrpll=args.with_wrpll,
|
|
**soc_sayma_amc_argdict(args))
|
|
elif variant == "simplesatellite":
|
|
soc = SimpleSatellite(with_wrpll=args.with_wrpll, **soc_sayma_amc_argdict(args))
|
|
elif variant == "master":
|
|
soc = Master(**soc_sayma_amc_argdict(args))
|
|
else:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|