mirror of https://github.com/m-labs/artiq.git
402 lines
13 KiB
Python
402 lines
13 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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from artiq.gateware.serwb.kusphy import KUSSerdes
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from artiq.gateware.serwb.s7phy import S7Serdes
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# Master <--> Slave synchronization:
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# 1) Master sends idle pattern (zeroes) to reset Slave.
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# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern.
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# 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas.
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# 4) Master stops sending K28.5 commas.
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# 5) Slave stops sending K28.5 commas.
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# 6) Physical link is ready.
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@ResetInserter()
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class _SerdesMasterInit(Module):
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def __init__(self, serdes, taps, timeout=2**15):
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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self.submodules.timer = timer = WaitTimer(timeout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip, 0),
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NextState("RESET_SLAVE"),
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serdes.tx_idle.eq(1)
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)
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fsm.act("RESET_SLAVE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("SEND_PATTERN")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("SEND_PATTERN",
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If(~serdes.rx_idle,
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timer.wait.eq(1),
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If(timer.done,
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NextState("CHECK_PATTERN")
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)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
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NextState("CHECK_SAMPLING_WINDOW")
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).Else(
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NextState("INC_DELAY_BITSLIP")
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)
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),
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serdes.tx_comma.eq(1)
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)
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self.comb += serdes.rx_bitslip_value.eq(bitslip)
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fsm.act("INC_DELAY_BITSLIP",
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NextState("WAIT_STABLE"),
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If(delay == (taps - 1),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay_min_found, 0),
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NextValue(delay_min, 0),
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NextValue(delay_max_found, 0),
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NextValue(delay_max, 0),
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NextValue(bitslip, bitslip + 1)
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),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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# switch to next bitslip
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NextValue(delay, taps - 1),
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NextState("INC_DELAY_BITSLIP")
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).Else(
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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NextState("READY")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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@ResetInserter()
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class _SerdesSlaveInit(Module, AutoCSR):
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def __init__(self, serdes, taps, timeout=2**15):
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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self.submodules.timer = timer = WaitTimer(timeout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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# reset
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fsm.act("IDLE",
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip, 0),
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("WAIT_STABLE"),
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
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NextState("CHECK_SAMPLING_WINDOW")
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).Else(
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NextState("INC_DELAY_BITSLIP")
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)
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),
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serdes.tx_idle.eq(1)
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)
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self.comb += serdes.rx_bitslip_value.eq(bitslip)
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fsm.act("INC_DELAY_BITSLIP",
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NextState("WAIT_STABLE"),
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If(delay == (taps - 1),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay_min_found, 0),
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NextValue(delay_min, 0),
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NextValue(delay_max_found, 0),
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NextValue(delay_max, 0),
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NextValue(bitslip, bitslip + 1)
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),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1)
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_SAMPLING_WINDOW",
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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# switch to next bitslip
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NextValue(delay, taps - 1),
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NextState("INC_DELAY_BITSLIP")
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).Else(
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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NextState("SEND_PATTERN")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("SEND_PATTERN",
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If(~serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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NextState("READY")
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)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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class _SerdesControl(Module, AutoCSR):
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def __init__(self, serdes, init, mode="master"):
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if mode == "master":
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self.reset = CSR()
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self.ready = CSRStatus()
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self.error = CSRStatus()
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self.delay = CSRStatus(9)
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self.delay_min_found = CSRStatus()
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self.delay_min = CSRStatus(9)
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self.delay_max_found = CSRStatus()
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self.delay_max = CSRStatus(9)
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self.bitslip = CSRStatus(6)
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self.scrambling_enable = CSRStorage()
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self.prbs_error = Signal()
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self.prbs_start = CSR()
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self.prbs_cycles = CSRStorage(32)
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self.prbs_errors = CSRStatus(32)
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# # #
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if mode == "master":
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# In Master mode, reset is coming from CSR,
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# it resets the Master that will also reset
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# the Slave by putting the link in idle.
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self.sync += init.reset.eq(self.reset.re)
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else:
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# In Slave mode, reset is coming from link,
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# Master reset the Slave by putting the link
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# in idle.
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self.sync += [
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init.reset.eq(serdes.rx_idle),
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serdes.reset.eq(serdes.rx_idle)
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]
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self.comb += [
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self.ready.status.eq(init.ready),
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self.error.status.eq(init.error),
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self.delay.status.eq(init.delay),
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self.delay_min_found.status.eq(init.delay_min_found),
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self.delay_min.status.eq(init.delay_min),
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self.delay_max_found.status.eq(init.delay_max_found),
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self.delay_max.status.eq(init.delay_max),
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self.bitslip.status.eq(init.bitslip)
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]
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# prbs
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prbs_cycles = Signal(32)
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prbs_errors = self.prbs_errors.status
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prbs_fsm = FSM(reset_state="IDLE")
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self.submodules += prbs_fsm
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prbs_fsm.act("IDLE",
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NextValue(prbs_cycles, 0),
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If(self.prbs_start.re,
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NextValue(prbs_errors, 0),
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NextState("CHECK")
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)
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)
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prbs_fsm.act("CHECK",
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NextValue(prbs_cycles, prbs_cycles + 1),
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If(self.prbs_error,
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NextValue(prbs_errors, prbs_errors + 1),
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),
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If(prbs_cycles == self.prbs_cycles.storage,
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NextState("IDLE")
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)
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)
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class SERWBPHY(Module, AutoCSR):
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def __init__(self, device, pads, mode="master", init_timeout=2**15):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("data", 32)])
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assert mode in ["master", "slave"]
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if device[:4] == "xcku":
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taps = 512
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self.submodules.serdes = KUSSerdes(pads, mode)
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elif device[:4] == "xc7a":
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taps = 32
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self.submodules.serdes = S7Serdes(pads, mode)
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else:
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raise NotImplementedError
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if mode == "master":
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self.submodules.init = _SerdesMasterInit(self.serdes, taps, init_timeout)
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else:
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self.submodules.init = _SerdesSlaveInit(self.serdes, taps, init_timeout)
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self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
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# scrambling
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scrambler = Scrambler()
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descrambler = Descrambler()
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self.submodules += scrambler, descrambler
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self.comb += [
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scrambler.enable.eq(self.control.scrambling_enable.storage),
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descrambler.enable.eq(self.control.scrambling_enable.storage)
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]
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# tx dataflow
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self.comb += \
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If(self.init.ready,
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sink.connect(scrambler.sink),
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scrambler.source.ack.eq(self.serdes.tx_ce),
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If(scrambler.source.stb,
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self.serdes.tx_d.eq(scrambler.source.d),
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self.serdes.tx_k.eq(scrambler.source.k)
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)
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)
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# rx dataflow
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self.comb += [
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If(self.init.ready,
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descrambler.sink.stb.eq(self.serdes.rx_ce),
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descrambler.sink.d.eq(self.serdes.rx_d),
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descrambler.sink.k.eq(self.serdes.rx_k),
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descrambler.source.connect(source)
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),
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# For PRBS test we are using the scrambler/descrambler as PRBS,
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# sending 0 to the scrambler and checking that descrambler
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# output is always 0.
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self.control.prbs_error.eq(
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descrambler.source.stb &
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descrambler.source.ack &
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(descrambler.source.data != 0))
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]
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