mirror of https://github.com/m-labs/artiq
90 lines
2.4 KiB
Python
90 lines
2.4 KiB
Python
import unittest
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from migen import *
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from artiq.gateware import rtio
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio.input_collector import *
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class OscInput(Module):
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def __init__(self):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(1),
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rtlink.IInterface(1))
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self.overrides = []
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self.probes = []
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# # #
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counter = Signal(2)
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trigger = Signal()
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self.sync += [
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Cat(counter, trigger).eq(counter + 1),
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self.rtlink.i.stb.eq(0),
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If(trigger,
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self.rtlink.i.stb.eq(1),
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self.rtlink.i.data.eq(~self.rtlink.i.data)
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)
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]
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class DUT(Module):
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def __init__(self):
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self.submodules.phy0 = OscInput()
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self.submodules.phy1 = OscInput()
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rtio_channels = [
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rtio.Channel.from_phy(self.phy0, ififo_depth=4),
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rtio.Channel.from_phy(self.phy1, ififo_depth=4)
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]
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self.submodules.tsc = rtio.TSC()
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self.submodules.input_collector = InputCollector(self.tsc, rtio_channels)
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@property
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def cri(self):
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return self.input_collector.cri
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def simulate(wait_cycles, ts_timeouts):
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result = []
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dut = DUT()
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def gen():
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for _ in range(wait_cycles):
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yield
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for ts_timeout in ts_timeouts:
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yield dut.cri.i_timeout.eq(ts_timeout)
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yield dut.cri.cmd.eq(cri.commands["read"])
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yield
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yield dut.cri.cmd.eq(cri.commands["nop"])
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yield
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while (yield dut.cri.i_status) & 4:
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yield
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status = yield dut.cri.i_status
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if status & 2:
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result.append("overflow")
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elif status & 1:
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result.append("timeout")
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else:
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i_timestamp = yield dut.cri.i_timestamp
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i_data = yield dut.cri.i_data
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result.append((i_timestamp, i_data))
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run_simulation(dut, gen())
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return result
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class TestInput(unittest.TestCase):
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def test_get_data(self):
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result = simulate(0, [256]*8)
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self.assertEqual(result, [(n*4+1, n % 2) for n in range(1, 9)])
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def test_timeout(self):
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result = simulate(0, [3, 16])
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self.assertEqual(result, ["timeout", (5, 1)])
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def test_overflow(self):
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result = simulate(32, [256])
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self.assertEqual(result, ["overflow"])
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