mirror of https://github.com/m-labs/artiq
118 lines
3.8 KiB
Python
118 lines
3.8 KiB
Python
from migen import *
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from artiq.gateware.rtio.phy import ttl_serdes_generic
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class _OSERDESE2_8X(Module):
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def __init__(self, invert=False):
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self.ser_out = Signal()
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self.o = Signal(8)
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self.t_in = Signal()
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self.t_out = Signal()
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# # #
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o = self.o
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b11111111 if invert else 0b00000000,
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o_OQ=self.ser_out, o_TQ=self.t_out,
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i_RST=ResetSignal("rio_phy"),
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i_CLK=ClockSignal("sys4x"),
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i_CLKDIV=ClockSignal("rio_phy"),
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i_D1=o[0] ^ invert, i_D2=o[1] ^ invert, i_D3=o[2] ^ invert, i_D4=o[3] ^ invert,
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i_D5=o[4] ^ invert, i_D6=o[5] ^ invert, i_D7=o[6] ^ invert, i_D8=o[7] ^ invert,
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i_TCE=1, i_OCE=1,
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i_T1=self.t_in)
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class _ISERDESE2_8X(Module):
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def __init__(self):
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self.ser_in = Signal()
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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# # #
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i = self.i
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self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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p_DATA_WIDTH=8,
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p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
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o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
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i_D=self.ser_in,
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i_CLK=ClockSignal("sys4x"),
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i_CLKB=~ClockSignal("sys4x"),
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i_CE1=1,
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i_RST=ResetSignal("rio_phy"),
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i_CLKDIV=ClockSignal("rio_phy"))
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class _IOSERDESE2_8X(Module):
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def __init__(self):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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# # #
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iserdes = _ISERDESE2_8X()
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oserdes = _OSERDESE2_8X()
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self.submodules += iserdes, oserdes
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self.comb += [
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self.i.eq(iserdes.i),
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oserdes.o.eq(self.o),
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oserdes.t_in.eq(~self.oe),
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]
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self.ser_out = oserdes.ser_out
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self.ser_in = iserdes.ser_in
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self.t_out = oserdes.t_out
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class Output_8X(ttl_serdes_generic.Output):
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def __init__(self, pad, pad_n=None, invert=False, dci=False):
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serdes = _OSERDESE2_8X(invert)
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self.submodules += serdes
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ttl_serdes_generic.Output.__init__(self, serdes)
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if pad_n is None:
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self.comb += pad.eq(serdes.ser_out)
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else:
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self.specials += Instance("IOBUFDS",
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i_I=serdes.ser_out,
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i_T=serdes.t_out,
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io_IO=pad, io_IOB=pad_n)
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class InOut_8X(ttl_serdes_generic.InOut):
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def __init__(self, pad, pad_n=None, dci=False):
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serdes = _IOSERDESE2_8X()
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self.submodules += serdes
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ttl_serdes_generic.InOut.__init__(self, serdes)
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if pad_n is None:
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self.specials += Instance("IOBUF",
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i_I=serdes.ser_out, o_O=serdes.ser_in, i_T=serdes.t_out,
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io_IO=pad)
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else:
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if dci:
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self.specials += Instance("IOBUFDS_DCIEN",
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p_DIFF_TERM="TRUE",
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p_IBUF_LOW_PWR="TRUE",
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p_USE_IBUFDISABLE="TRUE",
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i_IBUFDISABLE=~serdes.t_out,
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i_DCITERMDISABLE=~serdes.t_out,
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i_I=serdes.ser_out, o_O=serdes.ser_in, i_T=serdes.t_out,
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io_IO=pad, io_IOB=pad_n)
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else:
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self.specials += Instance("IOBUFDS_INTERMDISABLE",
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p_DIFF_TERM="TRUE",
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p_IBUF_LOW_PWR="TRUE",
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p_USE_IBUFDISABLE="TRUE",
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i_IBUFDISABLE=~serdes.t_out,
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i_INTERMDISABLE=~serdes.t_out,
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i_I=serdes.ser_out, o_O=serdes.ser_in, i_T=serdes.t_out,
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io_IO=pad, io_IOB=pad_n)
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