mirror of https://github.com/m-labs/artiq.git
122 lines
4.1 KiB
Python
122 lines
4.1 KiB
Python
from migen import *
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from migen.genlib.record import Record
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import BlindTransfer
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio import rtlink
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__all__ = ["InputCollector"]
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def get_channel_layout(coarse_ts_width, interface):
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data_width = rtlink.get_data_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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layout = []
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if data_width:
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layout.append(("data", data_width))
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if interface.timestamped:
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layout.append(("timestamp", coarse_ts_width + fine_ts_width))
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return layout
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class InputCollector(Module):
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def __init__(self, tsc, channels, quash_channels=[], interface=None):
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if interface is None:
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interface = cri.Interface()
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self.cri = interface
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# # #
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i_statuses, i_datas, i_timestamps = [], [], []
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i_ack = Signal()
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sel = self.cri.chan_sel[:16]
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for n, channel in enumerate(channels):
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iif = channel.interface.i
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if iif is None or n in quash_channels:
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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continue
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# FIFO
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layout = get_channel_layout(len(tsc.coarse_ts), iif)
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fifo = SyncFIFOBuffered(layout_len(layout), channel.ififo_depth)
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self.submodules += fifo
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fifo_in = Record(layout)
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fifo_out = Record(layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# FIFO write
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if iif.delay:
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counter_rtio = Signal.like(tsc.coarse_ts, reset_less=True)
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self.sync += counter_rtio.eq(tsc.coarse_ts - (iif.delay + 1))
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else:
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counter_rtio = tsc.coarse_ts
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if hasattr(fifo_in, "data"):
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self.comb += fifo_in.data.eq(iif.data)
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if hasattr(fifo_in, "timestamp"):
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if hasattr(iif, "fine_ts"):
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full_ts = Cat(iif.fine_ts, counter_rtio)
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else:
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full_ts = counter_rtio
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(iif.stb)
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overflow_trigger = Signal()
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self.comb += overflow_trigger.eq(fifo.we & ~fifo.writable)
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# FIFO read, CRI connection
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if hasattr(fifo_out, "data"):
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i_datas.append(fifo_out.data)
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else:
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i_datas.append(0)
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if hasattr(fifo_out, "timestamp"):
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ts_shift = 64 - len(fifo_out.timestamp)
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i_timestamps.append(fifo_out.timestamp << ts_shift)
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else:
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i_timestamps.append(0)
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selected = Signal()
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self.comb += selected.eq(sel == n)
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overflow = Signal()
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self.sync += [
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If(selected & i_ack,
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overflow.eq(0)),
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If(overflow_trigger,
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overflow.eq(1))
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]
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self.comb += fifo.re.eq(selected & i_ack & ~overflow)
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i_statuses.append(Cat(fifo.readable & ~overflow, overflow))
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i_status_raw = Signal(2)
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self.comb += i_status_raw.eq(Array(i_statuses)[sel])
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input_timeout = Signal.like(self.cri.i_timeout, reset_less=True)
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input_pending = Signal()
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self.cri.i_data.reset_less = True
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self.cri.i_timestamp.reset_less = True
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self.sync += [
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i_ack.eq(0),
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If(i_ack,
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self.cri.i_status.eq(Cat(~i_status_raw[0], i_status_raw[1], 0)),
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self.cri.i_data.eq(Array(i_datas)[sel]),
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self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
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),
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If((tsc.full_ts_cri >= input_timeout) | (i_status_raw != 0),
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If(input_pending, i_ack.eq(1)),
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input_pending.eq(0)
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),
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If(self.cri.cmd == cri.commands["read"],
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input_timeout.eq(self.cri.i_timeout),
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input_pending.eq(1),
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self.cri.i_status.eq(0b100)
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)
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]
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