mirror of https://github.com/m-labs/artiq
242 lines
7.8 KiB
Python
242 lines
7.8 KiB
Python
"""Common RTIO Interface"""
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from migen import *
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from migen.genlib.record import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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# CRI write happens in 3 cycles:
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# 1. set timestamp and channel
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# 2. set other payload elements and issue write command
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# 3. check status
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commands = {
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"nop": 0,
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"write": 1,
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# i_status should have the "wait for status" bit set until
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# an event is available, or timestamp is reached.
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"read": 2,
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# targets must assert o_buffer_space_valid in response
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# to this command
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"get_buffer_space": 3
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}
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layout = [
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("cmd", 2, DIR_M_TO_S),
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# 8 MSBs of chan_sel = routing destination
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# 16 LSBs of chan_sel = channel within the destination
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("chan_sel", 24, DIR_M_TO_S),
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("o_timestamp", 64, DIR_M_TO_S),
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("o_data", 512, DIR_M_TO_S),
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("o_address", 8, DIR_M_TO_S),
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# o_status bits:
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# <0:wait> <1:underflow> <2:destination unreachable>
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("o_status", 3, DIR_S_TO_M),
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# pessimistic estimate of the number of outputs events that can be
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# written without waiting.
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# this feature may be omitted on systems without DRTIO.
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("o_buffer_space_valid", 1, DIR_S_TO_M),
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("o_buffer_space", 16, DIR_S_TO_M),
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("i_timeout", 64, DIR_M_TO_S),
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("i_data", 32, DIR_S_TO_M),
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("i_timestamp", 64, DIR_S_TO_M),
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# i_status bits:
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# <0:wait for event (command timeout)> <1:overflow> <2:wait for status>
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# <3:destination unreachable>
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# <0> and <1> are mutually exclusive. <1> has higher priority.
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("i_status", 4, DIR_S_TO_M),
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]
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class Interface(Record):
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def __init__(self, **kwargs):
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Record.__init__(self, layout, **kwargs)
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, tsc, cri=None, now64=False):
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self.target = CSRStorage(32)
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if now64:
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self.now = CSRStorage(64)
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else:
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# not using CSRStorage atomic_write feature here to make storage reset_less
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self.now_hi = CSR(32)
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self.now_lo = CSR(32)
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# Writing target clears o_data. This implements automatic
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# zero-extension of output event data by the gateware. When staging an
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# output event, always write target before o_data.
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self.o_data = CSRStorage(512, write_from_dev=True)
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self.o_status = CSRStatus(3)
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self.i_timeout = CSRStorage(64)
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self.i_data = CSRStatus(32)
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self.i_timestamp = CSRStatus(64)
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self.i_status = CSRStatus(4)
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self.counter = CSRStatus(64)
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self.counter_update = CSR()
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if cri is None:
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cri = Interface()
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self.cri = cri
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# # #
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if now64:
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now = self.now.storage
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else:
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now = Signal(64, reset_less=True)
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now_hi_backing = Signal(32)
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self.sync += [
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If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)),
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If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing)))
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]
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self.comb += [
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self.now_hi.w.eq(now[32:]),
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self.now_lo.w.eq(now[:32])
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]
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self.comb += [
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self.cri.cmd.eq(commands["nop"]),
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If(self.o_data.re, self.cri.cmd.eq(commands["write"])),
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If(self.i_timeout.re, self.cri.cmd.eq(commands["read"])),
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self.cri.chan_sel.eq(self.target.storage[8:]),
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self.cri.o_timestamp.eq(now),
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self.cri.o_data.eq(self.o_data.storage),
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self.cri.o_address.eq(self.target.storage[:8]),
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self.o_status.status.eq(self.cri.o_status),
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self.cri.i_timeout.eq(self.i_timeout.storage),
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self.i_data.status.eq(self.cri.i_data),
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self.i_timestamp.status.eq(self.cri.i_timestamp),
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self.i_status.status.eq(self.cri.i_status),
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self.o_data.dat_w.eq(0),
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self.o_data.we.eq(self.target.re),
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]
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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class CRIDecoder(Module):
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def __init__(self, slaves=2, master=None, enable_routing=False):
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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if master is None:
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master = Interface()
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self.slaves = slaves
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self.master = master
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# # #
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# routing
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if enable_routing:
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destination_unreachable = Interface()
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self.comb += [
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destination_unreachable.o_status.eq(4),
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destination_unreachable.i_status.eq(8)
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]
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slaves = slaves[:]
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slaves.append(destination_unreachable)
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target_len = 2**(len(slaves) - 1).bit_length()
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slaves += [destination_unreachable]*(target_len - len(slaves))
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slave_bits = bits_for(len(slaves)-1)
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selected = Signal(slave_bits)
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if enable_routing:
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self.specials.routing_table = Memory(slave_bits, 256)
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rtp_decoder = self.routing_table.get_port()
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self.specials += rtp_decoder
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self.comb += [
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rtp_decoder.adr.eq(self.master.chan_sel[16:]),
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selected.eq(rtp_decoder.dat_r)
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]
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else:
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self.sync += selected.eq(self.master.chan_sel[16:])
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# master -> slave
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for n, slave in enumerate(slaves):
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for name, size, direction in layout:
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if direction == DIR_M_TO_S and name != "cmd":
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self.comb += getattr(slave, name).eq(getattr(master, name))
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self.comb += If(selected == n, slave.cmd.eq(master.cmd))
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# slave -> master
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cases = dict()
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for n, slave in enumerate(slaves):
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cases[n] = []
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for name, size, direction in layout:
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if direction == DIR_S_TO_M:
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cases[n].append(getattr(master, name).eq(getattr(slave, name)))
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self.comb += Case(selected, cases)
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class CRISwitch(Module, AutoCSR):
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def __init__(self, masters=2, slave=None):
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if isinstance(masters, int):
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masters = [Interface() for _ in range(masters)]
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if slave is None:
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slave = Interface()
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self.masters = masters
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self.slave = slave
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self.selected = CSRStorage(len(masters).bit_length())
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# # #
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if len(masters) == 1:
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self.comb += masters[0].connect(slave)
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else:
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# mux master->slave signals
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for name, size, direction in layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(slave, name).eq(choices[self.selected.storage])
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# connect slave->master signals
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for name, size, direction in layout:
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if direction == DIR_S_TO_M:
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source = getattr(slave, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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self.comb += dest.eq(source)
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class CRIInterconnectShared(Module):
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def __init__(self, masters=2, slaves=2, enable_routing=False):
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shared = Interface()
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self.submodules.switch = CRISwitch(masters, shared)
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self.submodules.decoder = CRIDecoder(slaves, shared, enable_routing)
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def get_csrs(self):
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return self.switch.get_csrs()
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class RoutingTableAccess(Module, AutoCSR):
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def __init__(self, interconnect):
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if isinstance(interconnect, CRIInterconnectShared):
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interconnect = interconnect.decoder
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rtp_csr = interconnect.routing_table.get_port(write_capable=True)
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self.specials += rtp_csr
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self.destination = CSRStorage(8)
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self.hop = CSR(len(rtp_csr.dat_w))
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self.comb += [
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rtp_csr.adr.eq(self.destination.storage),
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rtp_csr.dat_w.eq(self.hop.r),
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rtp_csr.we.eq(self.hop.re),
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self.hop.w.eq(rtp_csr.dat_r)
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]
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