mirror of https://github.com/m-labs/artiq.git
63 lines
2.1 KiB
Python
63 lines
2.1 KiB
Python
from migen import *
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from migen.genlib.cdc import ElasticBuffer
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class GenericRXSynchronizer(Module):
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"""Simple RX synchronizer based on the portable Migen elastic buffer.
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Introduces timing non-determinism in the satellite RX path, e.g.
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echo_request/echo_reply RTT and TSC sync, but useful for testing.
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"""
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def __init__(self):
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self.signals = []
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def resync(self, signal):
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synchronized = Signal.like(signal, related=signal)
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self.signals.append((signal, synchronized))
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return synchronized
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def do_finalize(self):
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eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "sys")
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self.submodules += eb
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self.comb += [
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eb.din.eq(Cat(*[s[0] for s in self.signals])),
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Cat(*[s[1] for s in self.signals]).eq(eb.dout)
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]
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class XilinxRXSynchronizer(Module):
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"""Deterministic RX synchronizer using a relatively placed macro
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to put the clock-domain-crossing FFs right next to each other.
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To meet setup/hold constraints at the receiving FFs, adjust the phase shift
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of the jitter cleaner.
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We assume that FPGA routing variations are small enough to be negligible.
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"""
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def __init__(self):
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self.signals = []
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def resync(self, signal):
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synchronized = Signal.like(signal, related=signal)
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self.signals.append((signal, synchronized))
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return synchronized
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def do_finalize(self):
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l = sum(len(s[0]) for s in self.signals)
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din = Signal(l)
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inter = Signal(l)
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dout = Signal(l)
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self.comb += [
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din.eq(Cat(*[s[0] for s in self.signals])),
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Cat(*[s[1] for s in self.signals]).eq(dout)
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]
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for i in range(l):
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hu_set = ("HU_SET", "drtio_rx_synchronizer")
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self.specials += [
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Instance("FD", i_C=ClockSignal("rtio_rx"), i_D=din[i], o_Q=inter[i],
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attr={hu_set, ("RLOC", "X0Y{}".format(i))}),
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Instance("FD", i_C=ClockSignal("sys"), i_D=inter[i], o_Q=dout[i],
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attr={hu_set, ("RLOC", "X1Y{}".format(i))})
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]
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