mirror of https://github.com/m-labs/artiq
265 lines
8.8 KiB
Rust
265 lines
8.8 KiB
Rust
use board_misoc::config;
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#[cfg(si5324_as_synthesizer)]
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use board_artiq::si5324;
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use board_misoc::{csr, clock};
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#[derive(Debug, PartialEq)]
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#[allow(non_camel_case_types)]
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pub enum RtioClock {
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Default,
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Int_125,
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Int_100,
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Ext0_Bypass,
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Ext0_Synth0_10to125,
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Ext0_Synth0_100to125,
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Ext0_Synth0_125to125,
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}
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#[allow(unreachable_code)]
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fn get_rtio_clock_cfg() -> RtioClock {
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config::read_str("rtio_clock", |result| {
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let res = match result {
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Ok("int_125") => RtioClock::Int_125,
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Ok("int_100") => RtioClock::Int_100,
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Ok("ext0_bypass") => RtioClock::Ext0_Bypass,
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Ok("ext0_bypass_125") => RtioClock::Ext0_Bypass,
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Ok("ext0_bypass_100") => RtioClock::Ext0_Bypass,
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Ok("ext0_synth0_10to125") => RtioClock::Ext0_Synth0_10to125,
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Ok("ext0_synth0_100to125") => RtioClock::Ext0_Synth0_100to125,
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Ok("ext0_synth0_125to125") => RtioClock::Ext0_Synth0_125to125,
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Ok("i") => {
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warn!("Using legacy rtio_clock setting ('i'). Falling back to default. This will be deprecated.");
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RtioClock::Default
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},
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Ok("e") => {
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warn!("Using legacy rtio_clock setting ('e'). This will be deprecated.");
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RtioClock::Ext0_Bypass
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},
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_ => {
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warn!("rtio_clock setting not recognised. Falling back to default.");
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RtioClock::Default
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}
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};
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if res == RtioClock::Default {
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#[cfg(any(si5324_ext_ref, ext_ref_frequency))]
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warn!("si5324_ext_ref and ext_ref_frequency compile-time options are deprecated. Please use the rtio_clock coreconfig settings instead.");
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "10.0"))]
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return RtioClock::Ext0_Synth0_10to125;
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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return RtioClock::Ext0_Synth0_100to125;
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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return RtioClock::Ext0_Synth0_125to125;
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#[cfg(all(rtio_frequency = "125.0", not(si5324_ext_ref)))]
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return RtioClock::Int_125;
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#[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref), not(soc_platform = "kasli")))]
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return RtioClock::Int_100;
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//in case nothing is set
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return RtioClock::Int_125;
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}
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res
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})
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}
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#[cfg(has_rtio_crg)]
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pub mod crg {
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use board_misoc::{clock, csr};
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pub fn check() -> bool {
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unsafe { csr::rtio_crg::pll_locked_read() != 0 }
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}
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pub fn init() -> bool {
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info!("Using internal RTIO clock");
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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}
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#[cfg(not(has_rtio_crg))]
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pub mod crg {
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pub fn check() -> bool { true }
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}
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// Si5324 input to select for locking to an external clock (as opposed to
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// a recovered link clock in DRTIO satellites, which is handled elsewhere).
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#[cfg(all(si5324_as_synthesizer, soc_platform = "kasli", hw_rev = "v2.0"))]
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const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
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#[cfg(all(si5324_as_synthesizer, soc_platform = "kasli", not(hw_rev = "v2.0")))]
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const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
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#[cfg(all(si5324_as_synthesizer, soc_platform = "kc705"))]
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const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer(cfg: RtioClock) {
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let (si5324_settings, si5324_ref_input) = match cfg {
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RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 300,
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n31 : 6,
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n32 : 6,
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bwsel : 4,
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crystal_as_ckin2: false
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 260,
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n31 : 52,
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n32 : 52,
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bwsel : 4,
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crystal_as_ckin2: false
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 8,
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n2_hs : 7,
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n2_ls : 360,
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n31 : 63,
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n32 : 63,
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bwsel : 4,
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crystal_as_ckin2: false
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Int_100 => { // 100MHz output, from crystal
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info!("using internal 100MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 7139,
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n32 : 7139,
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bwsel : 3,
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crystal_as_ckin2: true
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},
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si5324::Input::Ckin2
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)
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},
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RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
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info!("using internal 125MHz RTIO clock");
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_as_ckin2: true
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},
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si5324::Input::Ckin2
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)
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},
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_ => { // 125MHz output like above, default (if chosen option is not supported)
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warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg);
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(
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si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 19972,
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n31 : 4565,
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n32 : 4565,
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bwsel : 4,
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crystal_as_ckin2: true
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},
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si5324::Input::Ckin2
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)
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}
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};
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si5324::setup(&si5324_settings, si5324_ref_input).expect("cannot initialize Si5324");
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}
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fn setup_si5324(clock_cfg: RtioClock) {
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let switched = unsafe {
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csr::crg::switch_done_read()
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};
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if switched == 1 {
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info!("Clocking has already been set up.");
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return;
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}
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match clock_cfg {
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RtioClock::Ext0_Bypass => {
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info!("using external RTIO clock with PLL bypass");
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si5324::bypass(SI5324_EXT_INPUT).expect("cannot bypass Si5324")
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},
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_ => setup_si5324_as_synthesizer(clock_cfg),
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}
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// switch sysclk source to si5324
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#[cfg(not(has_drtio))]
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{
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info!("Switching sys clock, rebooting...");
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// delay for clean UART log, wait until UART FIFO is empty
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clock::spin_us(1300);
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unsafe {
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csr::crg::clock_sel_write(1);
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loop {}
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}
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}
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}
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pub fn init() {
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let clock_cfg = get_rtio_clock_cfg();
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setup_si5324(clock_cfg);
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#[cfg(has_drtio)]
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{
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let switched = unsafe {
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csr::crg::switch_done_read()
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};
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if switched == 0 {
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info!("Switching sys clock, rebooting...");
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clock::spin_us(500); // delay for clean UART log
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unsafe {
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// clock switch and reboot will begin after TX is initialized
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// and TX will be initialized after this
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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loop {}
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}
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else {
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// enable TX after the reboot, with stable clock
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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}
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#[cfg(has_rtio_crg)]
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{
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let result = crg::init();
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if !result {
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error!("RTIO clock failed");
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}
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}
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}
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