mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-19 00:16:29 +08:00
34 lines
889 B
Python
34 lines
889 B
Python
from migen.fhdl.std import *
|
|
from migen.genlib.record import Record
|
|
|
|
|
|
def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
|
|
rbus = []
|
|
for pad in pads:
|
|
layout = [
|
|
("o_stb", 1),
|
|
("o_value", 2)
|
|
]
|
|
if fine_ts_bits:
|
|
layout.append(("o_fine_ts", fine_ts_bits))
|
|
if pad not in output_only_pads and pad not in mini_pads:
|
|
layout += [
|
|
("oe", 1),
|
|
("i_stb", 1),
|
|
("i_value", 1),
|
|
("i_pileup", 1)
|
|
]
|
|
if fine_ts_bits:
|
|
layout.append(("i_fine_ts", fine_ts_bits))
|
|
chif = Record(layout)
|
|
chif.mini = pad in mini_pads
|
|
rbus.append(chif)
|
|
return rbus
|
|
|
|
|
|
def get_fine_ts_width(rbus):
|
|
if hasattr(rbus[0], "o_fine_ts"):
|
|
return flen(rbus[0].o_fine_ts)
|
|
else:
|
|
return 0
|