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https://github.com/m-labs/artiq.git
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Sebastien Bourdeauducq
657afd770e
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
47 lines
1.1 KiB
Python
47 lines
1.1 KiB
Python
import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.accu import Accu, PhasedAccu
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from .tools import xfer
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def read(o, n):
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p = []
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for i in range(n):
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p.append((yield from [(yield pi) for pi in o.payload.flatten()]))
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yield
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return p
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def _test_gen_accu(dut, o):
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yield dut.o.ack.eq(1)
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yield from xfer(dut, i=dict(p=0, f=1, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=2, clr=0))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=2, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=8, f=-1, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=0, clr=1))
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yield from xfer(dut, i=dict(p=1, f=0, clr=0))
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o.extend((yield from read(dut.o, 8)))
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def _test_accu():
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dut = PhasedAccu(8, parallelism=8)
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if False:
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print(convert(dut))
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else:
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o = []
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run_simulation(dut, _test_gen_accu(dut, o), vcd_name="accu.vcd")
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o = np.array(o)
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print(o)
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if __name__ == "__main__":
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_test_accu()
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