mirror of https://github.com/m-labs/artiq.git
31 lines
1010 B
Python
31 lines
1010 B
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from artiqlib.rtio.rbus import create_rbus
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class SimplePHY(Module):
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def __init__(self, pads, output_only_pads=set(), mini_pads=set()):
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self.rbus = create_rbus(0, pads, output_only_pads, mini_pads)
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self.loopback_latency = 3
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# # #
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for pad, chif in zip(pads, self.rbus):
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o_pad = Signal()
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self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
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if hasattr(chif, "oe"):
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ts = TSTriple()
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i_pad = Signal()
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self.sync += ts.oe.eq(chif.oe)
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self.comb += ts.o.eq(o_pad)
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self.specials += MultiReg(ts.i, i_pad), \
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ts.get_tristate(pad)
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i_pad_d = Signal()
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self.sync += i_pad_d.eq(i_pad)
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self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
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chif.i_value.eq(i_pad)
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else:
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self.comb += pad.eq(o_pad)
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