mirror of https://github.com/m-labs/artiq
66 lines
2.2 KiB
Rust
66 lines
2.2 KiB
Rust
#[cfg(has_converter_spi)]
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mod imp {
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use board_misoc::csr;
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const INVALID_BUS: &'static str = "Invalid SPI bus";
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pub fn set_config(busno: u8, flags: u8, length: u8, div: u8, cs: u8) -> Result<(), &'static str> {
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if busno != 0 {
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return Err(INVALID_BUS)
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}
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::offline_write(flags >> 0 & 1);
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csr::converter_spi::end_write(flags >> 1 & 1);
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// input (in RTIO): flags >> 2 & 1
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// cs_polarity is a mask in the CSR interface
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// only affect the bits that are selected
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let mut cs_polarity = csr::converter_spi::cs_polarity_read();
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if flags >> 3 & 1 != 0 {
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cs_polarity |= cs;
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} else {
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cs_polarity &= !cs;
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}
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csr::converter_spi::cs_polarity_write(cs_polarity);
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csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
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csr::converter_spi::clk_phase_write(flags >> 5 & 1);
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csr::converter_spi::lsb_first_write(flags >> 6 & 1);
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csr::converter_spi::half_duplex_write(flags >> 7 & 1);
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csr::converter_spi::length_write(length - 1);
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csr::converter_spi::div_write(div - 2);
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csr::converter_spi::cs_write(cs);
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}
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Ok(())
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}
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pub fn write(busno: u8, data: u32) -> Result<(), &'static str> {
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if busno != 0 {
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return Err(INVALID_BUS)
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}
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unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_write(data);
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}
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Ok(())
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}
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pub fn read(busno: u8) -> Result<u32, &'static str> {
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if busno != 0 {
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return Err(INVALID_BUS)
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}
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Ok(unsafe {
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while csr::converter_spi::writable_read() == 0 {}
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csr::converter_spi::data_read()
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})
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}
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}
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#[cfg(not(has_converter_spi))]
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mod imp {
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pub fn set_config(_busno: u8, _flags: u8, _length: u8, _div: u8, _cs: u8) -> Result<(), ()> { Err(()) }
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pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
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pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
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}
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pub use self::imp::*;
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