mirror of https://github.com/m-labs/artiq
78 lines
2.4 KiB
Rust
78 lines
2.4 KiB
Rust
use spi;
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use board_misoc::{csr, clock};
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const DATA_CTRL_REG : u8 = 0x02;
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const IRCML_REG : u8 = 0x05;
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const QRCML_REG : u8 = 0x08;
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const CLKMODE_REG : u8 = 0x14;
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const VERSION_REG : u8 = 0x1F;
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const RETIMER_CLK_PHASE : u8 = 0b11;
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fn hard_reset() {
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unsafe {
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// Min Pulse Width: 50ns
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csr::dac_rst::out_write(1);
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clock::spin_us(1);
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csr::dac_rst::out_write(0);
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}
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}
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fn spi_setup(dac_sel: u8, half_duplex: bool, end: bool) -> Result<(), &'static str> {
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// Clear the cs_polarity and cs config
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spi::set_config(0, 0, 8, 64, 0b1111)?;
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spi::set_config(0, 1 << 3, 8, 64, (7 - dac_sel) << 1)?;
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spi::set_config(0, (half_duplex as u8) << 7 | (end as u8) << 1, 8, 64, 0b0001)?;
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Ok(())
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}
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fn write(dac_sel: u8, reg: u8, val: u8) -> Result<(), &'static str> {
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spi_setup(dac_sel, false, false)?;
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spi::write(0, (reg as u32) << 24)?;
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spi_setup(dac_sel, false, true)?;
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spi::write(0, (val as u32) << 24)?;
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Ok(())
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}
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fn read(dac_sel: u8, reg: u8) -> Result<u8, &'static str> {
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spi_setup(dac_sel, false, false)?;
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spi::write(0, ((reg | 1 << 7) as u32) << 24)?;
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spi_setup(dac_sel, true, true)?;
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spi::write(0, 0)?;
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Ok(spi::read(0)? as u8)
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}
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pub fn init() -> Result<(), &'static str> {
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hard_reset();
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for channel in 0..8 {
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let reg = read(channel, VERSION_REG)?;
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if reg != 0x0A {
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debug!("DAC AD9117 Channel {} has incorrect hardware version. VERSION reg: {:02x}", channel, reg);
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return Err("DAC AD9117 hardware version is not equal to 0x0A");
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}
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// Check for the presence of DCLKIO and CLKIN
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let reg = read(channel, CLKMODE_REG)?;
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if reg >> 4 & 1 != 0 {
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debug!("DAC AD9117 Channel {} retiming fails. CLKMODE reg: {:02x}", channel, reg);
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return Err("DAC AD9117 retiming failure");
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}
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// Force RETIMER-CLK to be Phase 1 as DCLKIO and CLKIN is known to be safe at Phase 1
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// See Issue #2200
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write(channel, CLKMODE_REG, RETIMER_CLK_PHASE << 6 | 1 << 2 | RETIMER_CLK_PHASE)?;
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// Set the DACs input data format to be twos complement
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// Set IFIRST and IRISING to True
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write(channel, DATA_CTRL_REG, 1 << 7 | 1 << 5 | 1 << 4)?;
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// Enable internal common mode resistors of both channels
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write(channel, IRCML_REG, 1 << 7)?;
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write(channel, QRCML_REG, 1 << 7)?;
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}
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Ok(())
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}
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