mirror of https://github.com/m-labs/artiq
137 lines
4.6 KiB
Python
137 lines
4.6 KiB
Python
class TRF372017:
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"""TRF372017 settings and register map.
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For possible values, documentation, and explanation, see the datasheet.
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https://www.ti.com/lit/gpn/trf372017
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"""
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rdiv = 2 # 13b - highest valid f_PFD
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ref_inv = 0
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neg_vco = 1
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icp = 0 # 1.94 mA, 5b
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icp_double = 0
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cal_clk_sel = 0b1110 # div64, 4b
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# default f_vco is 2.875 GHz
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nint = 23 # 16b - lowest value suitable for fractional & integer mode
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pll_div_sel = 0b01 # div2, 2b
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prsc_sel = 0 # 4/5
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vco_sel = 2 # 2b
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vcosel_mode = 0
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cal_acc = 0b00 # 2b
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en_cal = 0 # leave at 0 - calibration is performed in `Phaser.init()`
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nfrac = 0 # 25b
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pwd_pll = 0
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pwd_cp = 0
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pwd_vco = 0
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pwd_vcomux = 0
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pwd_div124 = 0
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pwd_presc = 0
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pwd_out_buff = 1 # leave at 1 - only enable outputs after calibration
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pwd_lo_div = 1 # leave at 1 - only enable outputs after calibration
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pwd_tx_div = 1 # leave at 1 - only enable outputs after calibration
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pwd_bb_vcm = 0
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pwd_dc_off = 0
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en_extvco = 0
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en_isource = 0
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ld_ana_prec = 0 # 2b
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cp_tristate = 0 # 2b
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speedup = 0
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ld_dig_prec = 1
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en_dith = 1
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mod_ord = 2 # 3rd order, 2b
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dith_sel = 0
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del_sd_clk = 2 # 2b
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en_frac = 0
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vcobias_rtrim = 4 # 3b
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pllbias_rtrim = 2 # 2b
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vco_bias = 8 # 460 µA, 4b
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vcobuf_bias = 2 # 2b
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vcomux_bias = 3 # 2b
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bufout_bias = 0 # 300 µA, 2b
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vco_cal_ib = 0 # PTAT
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vco_cal_ref = 2 # 1.04 V, 2b
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vco_ampl_ctrl = 3 # 2b
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vco_vb_ctrl = 0 # 1.2 V, 2b
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en_ld_isource = 0
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ioff = 0x80 # 8b
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qoff = 0x80 # 8b
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vref_sel = 4 # 0.85 V, 3b
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tx_div_sel = 0 # div1, 2b
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lo_div_sel = 0 # div1, 2b
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tx_div_bias = 1 # 37.5 µA, 2b
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lo_div_bias = 2 # 50 µA, 2b
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vco_trim = 0x20 # 6b
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vco_test_mode = 0
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cal_bypass = 0
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mux_ctrl = 1 # lock detect, 3b
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isource_sink = 0
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isource_trim = 4 # 3b
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pd_tc = 0 # 2b
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ib_vcm_sel = 0 # ptat
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dcoffset_i = 2 # 150 µA, 2b
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vco_bias_sel = 1 # spi
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def __init__(self, updates=None):
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if updates is None:
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return
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for key, value in updates.items():
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if not hasattr(self, key):
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raise KeyError("invalid setting", key)
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setattr(self, key, value)
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def get_mmap(self):
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"""Memory map for TRF372017"""
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mmap = []
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mmap.append(
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0x9 |
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(self.rdiv << 5) | (self.ref_inv << 19) | (self.neg_vco << 20) |
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(self.icp << 21) | (self.icp_double << 26) |
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(self.cal_clk_sel << 27))
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mmap.append(
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0xa |
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(self.nint << 5) | (self.pll_div_sel << 21) |
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(self.prsc_sel << 23) | (self.vco_sel << 26) |
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(self.vcosel_mode << 28) | (self.cal_acc << 29) |
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(self.en_cal << 31))
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mmap.append(0xb | (self.nfrac << 5))
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mmap.append(
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0xc |
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(self.pwd_pll << 5) | (self.pwd_cp << 6) | (self.pwd_vco << 7) |
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(self.pwd_vcomux << 8) | (self.pwd_div124 << 9) |
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(self.pwd_presc << 10) | (self.pwd_out_buff << 12) |
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(self.pwd_lo_div << 13) | (self.pwd_tx_div << 14) |
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(self.pwd_bb_vcm << 15) | (self.pwd_dc_off << 16) |
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(self.en_extvco << 17) | (self.en_isource << 18) |
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(self.ld_ana_prec << 19) | (self.cp_tristate << 21) |
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(self.speedup << 23) | (self.ld_dig_prec << 24) |
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(self.en_dith << 25) | (self.mod_ord << 26) |
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(self.dith_sel << 28) | (self.del_sd_clk << 29) |
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(self.en_frac << 31))
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mmap.append(
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0xd |
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(self.vcobias_rtrim << 5) | (self.pllbias_rtrim << 8) |
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(self.vco_bias << 10) | (self.vcobuf_bias << 14) |
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(self.vcomux_bias << 16) | (self.bufout_bias << 18) |
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(1 << 21) | (self.vco_cal_ib << 22) | (self.vco_cal_ref << 23) |
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(self.vco_ampl_ctrl << 26) | (self.vco_vb_ctrl << 28) |
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(self.en_ld_isource << 31))
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mmap.append(
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0xe |
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(self.ioff << 5) | (self.qoff << 13) | (self.vref_sel << 21) |
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(self.tx_div_sel << 24) | (self.lo_div_sel << 26) |
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(self.tx_div_bias << 28) | (self.lo_div_bias << 30))
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mmap.append(
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0xf |
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(self.vco_trim << 7) | (self.vco_test_mode << 14) |
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(self.cal_bypass << 15) | (self.mux_ctrl << 16) |
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(self.isource_sink << 19) | (self.isource_trim << 20) |
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(self.pd_tc << 23) | (self.ib_vcm_sel << 25) |
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(1 << 28) | (self.dcoffset_i << 29) |
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(self.vco_bias_sel << 31))
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return mmap
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