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646 Commits

Author SHA1 Message Date
hartytp fe63c9b366
SUServo: remove references to non-existent a0 parameter (#1268) 
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
 2019-02-07 15:29:32 +00:00
hartytp df6c1fca2c
SUServo: flake8 [NFC] (#1267) 
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
 2019-02-07 15:13:44 +00:00
Robert Jördens 8c5a502591 ad53xx: ignore F3 (reserved) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-24 15:50:46 +01:00
Sebastien Bourdeauducq 330c5610e9 ad9912: fix imports 2019-01-23 17:59:08 +08:00
Robert Jördens b692981c8e ad9910: add note about red front panel led 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 12:49:42 +01:00
Robert Jördens 91e375ce6a ad9910: don't reset the input divide-by-two 
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221;

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 09:37:20 +00:00
Robert Jördens 81ff3d4b29 ad9912: add some slack after init 2019-01-21 17:10:58 +00:00
Sebastien Bourdeauducq 84f7d006e8 ad9910: add precision about tune_io_update_delay/tune_sync_delay order 2019-01-21 19:40:55 +08:00
Sebastien Bourdeauducq 30051133b7 urukul: fix typos 2019-01-21 19:40:55 +08:00
Robert Jördens 40187d1957 ad9910: support configurable refclk divider and pll bypass 
for #1248

* also always keep refclk input divider (by two) reset
 2019-01-18 12:23:53 +00:00
Robert Jördens 385916a9a4 ad9912: support configurable clk_div 2019-01-18 12:16:08 +00:00
Robert Jördens 2bea5e3d58 urukul: support configurable refclk divider 
for #1248
 2019-01-18 12:09:32 +00:00
David Nadlinger a565f77538 Add gateware input event counter 2019-01-15 10:55:07 +00:00
David Nadlinger 6c52359e59 coredevice: Add _mu suffix to AD991x ref_time arguments 
GitHub: Fixes #1243.
 2019-01-12 17:34:35 +00:00
whitequark 49682d0159 Improve Python 3.7 compatibility. 
async is now a full (non-contextual) keyword.

There are two more instances:
   - artiq/frontend/artiq_client.py
   - artiq/devices/thorlabs_tcube/driver.py

It is not immediately clear how to fix those, so they are left for
later work.
 2019-01-12 13:17:59 +00:00
David Nadlinger 48fc175a6b coredevice.ttl: More imperative mood in docstrings [nfc] 
This follows Python conventions (PEP257) and unifies the style with
other comments.
 2019-01-12 12:01:55 +00:00
David Nadlinger 3e84ec2bf1 coredevice.ad9910: Fix phase tracking ref_time passing 
This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).

This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
 2019-01-12 00:47:38 +00:00
Robert Jördens 101671fbbf core_analyzer: support uniform VCD time intervals 
close #1236

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-10 19:35:09 +01:00
Robert Jördens 19748fe495 ad9910: fix RTIO fine timestamp nudging 
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.

close #1229

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 17:22:57 +00:00
Robert Jördens b25ab1fc88 ad9910: add more slack in tune_sync_delay 
close #1235

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 16:07:31 +00:00
Drew 40370c4d45 Docs: fix build warnings (#1234) 
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP

Found while building docs. Forgot to refactor strings.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>

* spi2: reformat update_xfer_duration_mu docstring

update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-09 11:39:23 +08:00
David Nadlinger 4fb434674d coredevice: Fix ad9910 __all__ exports 2019-01-08 18:55:26 +00:00
David Nadlinger cadde970e1 urukul: Expand CPLD sync_sel explanation [nfc] 2019-01-08 02:37:58 +00:00
David Nadlinger 7bcdeb825b ad9910: Add inverse FTW/ASF conversions 2019-01-08 02:18:14 +00:00
David Nadlinger 4d793d7149 ad9910: Truncate phase word to 16 bits 
This avoids overflowing into the asf portion of the register.
 2019-01-08 02:18:14 +00:00
Robert Jördens a7d4d3bda9 ad9910: CONT_RECIRCULATE -> CONT_RAMPUP 2018-12-17 13:25:00 +00:00
Sebastien Bourdeauducq 35bdf26f01 Merge branch 'ad9910-ram' 2018-12-17 21:16:44 +08:00
David Nadlinger e608d6ffd3 coredevice, firmware: Add rtio_input_timestamped_data 
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
 2018-12-15 00:35:04 +00:00
Robert Jördens 79eadb9465 ad9910: add RAM mode methods 
* also refactor the CFR1 access into a method

c.f. #1154

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 14:54:16 +00:00
Robert Jördens efd400b02c ad9910: style [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 11:36:25 +01:00
Robert Jördens d90eb3ae88 ad9910: add read64() 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:27:00 +00:00
Robert Jördens baf88050fd urukul: expand attenuator HITL unittests 
* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:06:12 +00:00
Sebastien Bourdeauducq dce4f036db grabber: work around windows numpy int peculiarity (same as a81c12de9) 2018-11-30 18:41:14 +08:00
Sebastien Bourdeauducq 450a035f9e suservo: move overflowing RTIO address bits into data 2018-11-26 06:54:20 +08:00
Sebastien Bourdeauducq b32e89444c Merge branch 'master' into new 2018-11-26 01:02:19 +08:00
Robert Jördens a81c12de94 urukul: work around windows numpy int peculiarity 
"OverflowError: Python int too large to convert to C long" otherwise

opticlock#74

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-25 16:56:45 +01:00
Sebastien Bourdeauducq 8f9858be4c ad9914: remove automatic continuous phase compensation (like Urukul) 2018-11-19 22:00:20 +08:00
Sebastien Bourdeauducq 53e79f553f Merge branch 'master' into new 2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq a3e0b1c5b4 ad9914,spi2: add warnings about driver state and DMA. Closes #1113 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq 69e699c7bd ttl: compensate for SED latency in input gating 
Closes #1137
 2018-11-17 22:10:20 +08:00
Robert Jördens 3ad68f65c5 urukul: make get_att_mu() not alter state 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 14:56:26 +00:00
Robert Jördens d1eee7c0ea ad9910: ensure sync is driven when required 
close #1194

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 13:21:01 +00:00
Sebastien Bourdeauducq 1b841805f6 Merge branch 'master' into new 2018-11-16 15:20:32 +08:00
Robert Jördens c3178c2cab ad9910: profile support 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 08:30:28 +01:00
Robert Jördens d0cadfeb4b ad9910: more idiomatic register names 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:55:01 +01:00
Robert Jördens a52d1be140 urukul: expose PROFILE setting 
* add documentation
* add unittest

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:43:56 +01:00
Robert Jördens a4997c56cf ad9910: simplify edge detection logic 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:54:34 +00:00
Robert Jördens 14b6b63916 ad9910: rewire io_delay tuning 
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:38:27 +00:00
Robert Jördens 38c6878d49 urukul: mention min/max attenuation 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:32:05 +01:00
Robert Jördens e565ca6b82 urukul: slow down att write to datasheet limit 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:23:06 +01:00