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39c6bc940c
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coreconfig: use new database API (closes #75)
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2015-07-17 10:49:55 +02:00 |
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9649e1837a
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gui: basic plotting
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2015-07-16 20:52:53 +02:00 |
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a83473a19a
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sync_struct: clarify notify_cb doc
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2015-07-16 20:52:27 +02:00 |
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Yann Sionneau
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78ee4bdb99
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pyqtgraph: use more up to date revision a6d5e28 on develop branch
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2015-07-16 20:00:08 +02:00 |
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whitequark
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2dcb744519
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Fix inference for default arguments.
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2015-07-16 17:26:31 +03:00 |
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whitequark
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f8e51e07d5
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Add zero/one accessors to TBool, TInt, TFloat.
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2015-07-16 16:03:24 +03:00 |
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whitequark
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bcd1832203
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Ensure bindings are created in correct order for e.g. "x, y = y, x".
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2015-07-16 15:59:59 +03:00 |
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whitequark
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5756cfcebc
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Correctly infer type of list(iterable).
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2015-07-16 15:35:46 +03:00 |
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whitequark
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6cda67c0c6
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Ensure type comparisons see through type variables.
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2015-07-16 14:59:05 +03:00 |
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whitequark
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c1e7a82e97
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Add IndexError and ValueError builtins.
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2015-07-16 14:58:40 +03:00 |
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whitequark
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b58fa9067d
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Add attributes to TRange.
Also make attributes an OrderedDict, for stable order during
LLVM IR generation.
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2015-07-16 14:57:44 +03:00 |
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whitequark
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a6950bf11d
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Move builtin.is_{builtin,exn_constructor} to types.
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2015-07-16 14:56:39 +03:00 |
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whitequark
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5000f87dfc
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Rename the field of CoerceT from expr to value.
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2015-07-16 14:55:23 +03:00 |
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whitequark
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e9416f4707
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Convert Slice into typed SliceT.
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2015-07-16 14:54:04 +03:00 |
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whitequark
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53fb03d1bf
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Restrict comprehensions to single for and no if clauses.
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2015-07-16 14:52:41 +03:00 |
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whitequark
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227f97f8a3
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Add inference for Index, Slice and ExtSlice.
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2015-07-16 04:22:41 +03:00 |
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66940ea815
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rtio: disable NOP suppression after reset and underflow
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2015-07-15 20:54:55 +02:00 |
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Yann Sionneau
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08eec40861
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manual: building LLVM as shared libraries is not recommended on Linux and not supported on Windows
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2015-07-15 17:34:06 +02:00 |
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Yann Sionneau
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774c66a209
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manual: also build LLVM native target (needed for py2llvm test)
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2015-07-15 17:32:32 +02:00 |
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Yann Sionneau
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fa4f38b871
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manual: add missing llvmlite patches
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2015-07-15 17:31:57 +02:00 |
|
Yann Sionneau
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511d51977e
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llvmlite: split patch to be cleaner. close #72
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2015-07-15 17:28:05 +02:00 |
|
Yann Sionneau
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af20efafa5
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conda: update llvmlite-or1k package and up the build number
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2015-07-15 17:28:05 +02:00 |
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f836465585
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coredevice: environment -> runtime
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2015-07-15 11:20:41 +02:00 |
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84de2fb28b
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expid: experiment -> class_name
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2015-07-15 11:08:12 +02:00 |
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255aba9247
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test/worker: remove stale handler
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2015-07-15 11:07:48 +02:00 |
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7de56666e3
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worker,environment: support scanning of arguments with no default
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2015-07-15 10:59:48 +02:00 |
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9ed4dcd7d1
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repository: load experiments in worker, list arguments
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2015-07-15 10:54:44 +02:00 |
|
whitequark
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c724e024ce
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Fix inference for multiple-target assignments.
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2015-07-15 06:33:44 +03:00 |
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7770ab64f2
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worker: factor timeouts
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2015-07-14 23:43:08 +02:00 |
|
whitequark
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9ff9f85f19
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Add accessors to instructions.
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2015-07-14 22:18:38 +03:00 |
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a07f2473b0
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manual: add core device moninj port
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2015-07-14 20:06:29 +02:00 |
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e20b260117
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gui: fix selections
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2015-07-14 19:08:08 +02:00 |
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21e8596d8c
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gui: RT results overview
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2015-07-14 17:31:18 +02:00 |
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55cd41444e
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gui/DictSync: better support of nested structs
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2015-07-14 17:30:55 +02:00 |
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1edeb5a13f
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sync_struct: docstring cleanup
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2015-07-14 17:30:21 +02:00 |
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84e7f55df3
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gui: fix DDS class recognition
|
2015-07-14 17:28:26 +02:00 |
|
Yann Sionneau
|
6e3fd591f7
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gui: remove unnecessary QSplitter
|
2015-07-14 16:59:04 +02:00 |
|
whitequark
|
bdcb24108b
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Add basic IR generator.
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2015-07-14 08:56:51 +03:00 |
|
whitequark
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f417ef31a4
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Make binop coercion look through CoerceT nodes.
This fixes inference for "x = 1 + 1" after int monomorphization.
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2015-07-14 06:42:09 +03:00 |
|
Yann Sionneau
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90ba9f7bbf
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llvmlite: rename our package to be llvmlite_or1k to avoid collision with llvmlite package needed for numba
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2015-07-14 01:01:56 +02:00 |
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56fc7a484c
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TTLInOut: timestamp -> timestamp_mu
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2015-07-13 23:21:29 +02:00 |
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820ff2da2c
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test/coredevice: WA for lack of constant string support in compiler (see issue #68)
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2015-07-13 22:22:26 +02:00 |
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32d141f5ac
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refactor ddb/pdb/rdb
|
2015-07-13 22:21:32 +02:00 |
|
whitequark
|
ebe243f8d9
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Add printing of SSA functions.
|
2015-07-13 21:08:20 +03:00 |
|
whitequark
|
dbdd45acc5
|
Add missing return.
|
2015-07-13 20:52:55 +03:00 |
|
whitequark
|
7c9afcce85
|
Fix Python default argument fiasco.
|
2015-07-13 20:52:48 +03:00 |
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8b02b58a77
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sync_struct/Notifier: do not pass root param to publish
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2015-07-13 17:12:59 +02:00 |
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0e92cfe053
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artiq_run: remove support for stale watchdog API
|
2015-07-11 22:26:37 +02:00 |
|
whitequark
|
7c52910dc5
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Add a basic SSA IR.
|
2015-07-11 18:46:37 +03:00 |
|
Yann Sionneau
|
01ca6ebb1c
|
binstar.org is becoming anaconda.org
|
2015-07-10 16:30:14 +02:00 |
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