whitequark
4804cfef9b
gateware: don't run tests if there is no migen.
...
This allows us to skip testing gateware on Windows.
2018-03-26 03:26:34 +00:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
1553fc8c7d
sed: reset valid in output sorter
2018-03-23 11:11:11 +00:00
770b0a7b79
novogorny: conv -> cnv
...
* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
1afce8c613
kasli: simplify single eem pin formatting
2018-03-21 13:08:42 +01:00
d48b8f3086
kasli: fix sampler sdr/cnv pins
2018-03-21 09:28:00 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
...
Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
...
This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
c8020f6bbd
ttl_serdes_generic: fix/upgrade test
2018-03-20 16:46:57 +08:00
a5825184b7
add ttl_serdes_ultrascale (untested)
2018-03-20 16:07:23 +08:00
fad066f1aa
ttl_serdes_7series: cleanup indentation
...
Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
Thomas Harty
37d431039d
Fix typos.
...
Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
2fdc180601
dsp/fir: outputs reset_less (pipelined)
2018-03-13 17:11:50 +00:00
2edf65f57b
drtio: fix satellite minimum_coarse_timestamp clock domain ( #947 )
2018-03-13 00:20:57 +08:00
1d081ed6c2
drtio: print diagnostic info on satellite write underflow ( #947 )
2018-03-12 23:41:19 +08:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
...
They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
3fbcf5f303
drtio: remove TSC correction ( #40 )
2018-03-09 10:36:17 +08:00
e38187c760
drtio: increase default underflow margin. Closes #947
2018-03-09 00:49:24 +08:00
8bd15d36c4
drtio: fix error CSR edge detection ( #947 )
2018-03-08 16:28:25 +08:00
82831a85b6
kasli/opticlock: add eem6 phys
2018-03-07 21:32:59 +01:00
3a6566f949
rtio: judicious spray with reset_less=True
...
Hoping to reduce rst routing difficulty and easier RTIO timing closure.
2018-03-07 14:57:18 +00:00
b0282fa855
spi2: reset configuration in rio_phy
2018-03-07 14:42:11 +00:00
4af7600b2d
Revert "LaneDistributor: try equivalent spread logic"
...
This reverts commit 8b70db5f17
2018-03-07 11:34:51 +00:00
a6d1b030c1
RTIO: use TS counter in the correct CD
...
artiq/m-labs#938
2018-03-07 11:34:42 +00:00
8b70db5f17
LaneDistributor: try equivalent spread logic
2018-03-07 11:34:42 +00:00
2cbd597416
LaneDistributor: style and signal consolidation [NFC]
2018-03-07 11:34:42 +00:00
916197c4d7
siphaser: cleanup
2018-03-07 11:15:44 +08:00
f7aba6b570
siphaser: fix phase_shift_done CSR
2018-03-07 10:57:30 +08:00
acfd9db185
siphaser: minor cleanup
2018-03-07 10:57:30 +08:00
7d98864b31
sayma: enable siphaser
2018-03-07 10:57:30 +08:00
a6e29462a8
sayma: enable multilink DRTIO
2018-03-07 10:57:30 +08:00
c34d00cbc9
drtio: implement Si5324 phaser gateware and partial firmware support
2018-03-07 10:57:30 +08:00
994ceca9ff
sayma_amc: disable slave fpga gateware loading
2018-03-06 17:27:43 +01:00
62af7fe2ac
Revert "kasli/opticlock: use plain ttls for channels 8-23"
...
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.
No decrease in power consumption or improvement in timing.
2018-03-06 14:27:19 +01:00
fd3cdce59a
kasli/opticlock: use plain ttls for channels 8-23
2018-03-06 14:27:19 +01:00
50298a6104
ttl_serdes_7series: suppress diff_term in outputs
2018-03-06 14:27:19 +01:00
e356150ac4
ttl_simple: support differential io
2018-03-06 14:27:19 +01:00
956098c213
kasli: add second urukul, make clk_sel drive optional
2018-03-06 14:26:27 +01:00
07de7af86a
kasli: make second eem optional in urukul
2018-03-06 14:26:26 +01:00
c25560baec
sed: more LaneDistributor comments
2018-03-06 20:56:35 +08:00
f40255c968
sed: add comments about key points in LaneDistributor
2018-03-06 20:51:09 +08:00
Florent Kermarrec
5b3d6d57e2
drtio/gth: power down rx on restart (seems to make link initialization reliable)
2018-03-06 11:49:28 +01:00
Florent Kermarrec
64b05f07bb
drtio/gth: use parameters from Xilinx transceiver wizard
2018-03-06 11:02:15 +01:00
Florent Kermarrec
45f1e5a70e
drtio/gth: cleanup import
2018-03-06 10:56:07 +01:00
6aaa8bf9d9
drtio: fix link error generation
2018-03-04 23:20:13 +08:00
d747d74cb3
test: fix test_dma
2018-03-04 23:19:06 +08:00
928d5dc9b3
drtio: raise RTIOLinkError if operation fails due to link lost ( #942 )
2018-03-04 01:02:53 +08:00
ddcc68cff9
sayma_amc: move bitstream options to migen
...
close #930
2018-03-02 18:13:03 +08:00
a9daaad77b
kasli: add SYSU variant and device_db
2018-03-02 14:44:31 +08:00
cc70578f1f
remove old spi RTIO Phy
2018-03-01 11:19:18 +01:00
ec5b81da55
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
...
* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
54984f080b
artiq_flash: flash RTM firmware
...
based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:29:01 +01:00
1f999c7f5f
sayma_amc: expose RTM fpga load pins as GPIOs
2018-02-28 18:44:36 +01:00
Florent Kermarrec
2896dc619b
drtio/transceiver/gth: fix multilane
2018-02-28 14:15:40 +01:00
386aa75aaa
kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master
2018-02-27 23:18:18 +08:00
5d81877b34
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
2018-02-27 23:15:20 +08:00
Florent Kermarrec
1f0d955ce4
drtio/transceiver/gtp: implement tx multi lane phase alignment sequence
2018-02-27 12:32:25 +01:00
e565d3fa59
kasli: add analyzer and RTIO log to DRTIO master target
2018-02-27 18:09:07 +08:00
Florent Kermarrec
5b0f9cc6fd
drtio/transceiver/gth: fix single transceiver case
2018-02-23 12:15:47 +01:00
Florent Kermarrec
b4ba71c7a4
drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...)
2018-02-23 08:37:05 +01:00
Florent Kermarrec
820c834251
drtio/transceiver/gth: implement tx multi lane phase alignment sequence
2018-02-22 22:14:15 +01:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
...
m-labs/artiq#687
2018-02-22 17:19:51 +01:00
3b7971d15d
kasli: spelling
2018-02-22 17:19:51 +01:00
771bf87b56
kc705: port amc101_dac/spi0 and sma_spi to spi2
2018-02-22 17:19:51 +01:00
f8e6b4f4e3
ad5360: port to spi2
...
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
...
Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
a63fd306af
urukul: use spi2
...
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
37a0d6580b
spi2: add RTIO gateware and coredevice driver
...
1006218997
2018-02-21 13:37:36 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7a1d71502a
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
2018-02-21 13:37:29 +00:00
476e4fdd56
ttl_serdes_7series: disable IBUF and INTERM when output
2018-02-21 13:37:29 +00:00
f060d6e1b3
drtio: increase A7 clock aligner check period
2018-02-20 18:50:35 +08:00
f15b4bdde7
style
2018-02-20 18:47:59 +08:00
7d9c7ada71
drtio: fix test infinite loop
2018-02-20 17:42:00 +08:00
ad2c9590d0
drtio: rewrite/fix reset and link bringup/teardown
2018-02-20 17:26:43 +08:00
7e02d8245c
kasli: false paths
...
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
...
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
52049cf36a
drtio: add Xilinx RX synchronizer
2018-02-19 17:49:43 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
Florent Kermarrec
f5831af535
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
2018-02-19 10:03:19 +01:00
Florent Kermarrec
89a158c0c9
drtio/transceiver/gtp_7series_init: remove dead code
2018-02-19 10:02:23 +01:00
Florent Kermarrec
782051f474
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
2018-02-19 09:59:50 +01:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
94c20dfd4d
drtio: fix misleading GenericRXSynchronizer comment
2018-02-19 00:47:54 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
287d533437
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908 "
...
This reverts commit 2d4a1340ea
2018-02-17 17:38:48 +08:00
73985a9215
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
2018-02-17 17:38:17 +08:00
039dee4c8e
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
...
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
2018-02-17 13:54:50 +08:00
cfb21ca126
si5324: fix usage of external CLKIN2 reference
2018-02-17 13:52:01 +08:00
e41f49cc75
kasli: opticlock 125 MHz, mark external reference case broken
2018-02-16 17:23:15 +00:00
4d42df2a7c
kasli: set up Si5324 in standalone operation
2018-02-15 20:32:58 +08:00
d7387611c0
sayma: print RTM gateware version
2018-02-15 19:31:58 +08:00
be693bc8a9
opticlock: examples
2018-02-13 22:13:40 +01:00
a3d136d30d
opticlock: wire urukul and novogorny
2018-02-13 22:13:40 +01:00
ab5f397fea
sed/fifos: use AsyncFIFOBuffered
...
(D)RTIO now passes timing at 150MHz on Kasli.
2018-02-13 20:02:51 +08:00
00f42f912b
rename 'RTM identifier' to 'RTM magic number'
...
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
2018-02-13 20:02:51 +08:00
96b948f57f
remote_csr: add sanity check of CSR CSV type column
2018-02-13 20:02:51 +08:00
Florent Kermarrec
bfdda340fd
drtio/transceiver/gtp_7series: use parameters from xilinx wizard
2018-02-13 00:23:59 +01:00
Florent Kermarrec
180c28551d
drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
2018-02-09 20:17:02 +01:00
2d4a1340ea
sayma_amc: remove RTM bitstream upload core. Closes #908
2018-02-07 12:27:35 +08:00
whitequark
61c64a76be
gateware: use a per-variant subfolder in --output-dir. ( fixes #912 )
...
This commit also adds support for --variant and --args
to artiq-devtool.
2018-02-06 08:19:01 +00:00
whitequark
885ab40946
conda: split RTM and AMC packages back.
...
This avoids multiplying the RTM compilation time by the number
of AMC packages.
2018-01-28 14:27:55 +00:00
whitequark
11a8b84355
Merge the build trees of sayma_amc and sayma_rtm targets.
...
This also makes them a single artiq_flash target, and a single
conda package.
2018-01-27 19:54:31 +00:00
440e19b8f9
kasli: use SFP2 for DRTIO mastering
...
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
2018-01-26 19:02:54 +08:00
e0e795f11c
sayma_amc: constrain pin, remove keep
2018-01-23 15:42:47 +00:00
b5c035bb52
sayma_rtm: constrain serwb clock input
2018-01-23 13:54:53 +00:00
aada38f508
kasli, kc705: remove vivado "keep", cleanup a constraint
2018-01-23 13:15:26 +00:00
85102e191e
sayma_rtm: derive clocks automatically
...
* also don't add false paths unless necessary
2018-01-23 11:00:55 +00:00
7d1b3f37c9
sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
2018-01-23 10:56:42 +00:00
649deccd9b
kasli: fix DRTIO satellite QPLL refclksel
2018-01-23 12:27:19 +08:00
4b4374f76a
sayma: register_jref for JESD204. Closes #904
2018-01-23 12:19:15 +08:00
763aefacff
kasli: fix typo
2018-01-23 12:10:54 +08:00
c7b148a704
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
2018-01-23 12:08:10 +08:00
d6157514c7
gtp_7series: flexible QPLL channel selection
2018-01-23 12:03:09 +08:00
9f87c34a94
kasli: fix QPLL instantiation
2018-01-23 10:39:31 +08:00
98a5607634
gtp_7series: set clock muxes correctly for second QPLL channel
2018-01-23 10:39:20 +08:00
25fee1a0bb
gtp_7series: use QPLL second channel
2018-01-23 10:15:49 +08:00
031d7ff020
kasli: keep using second QPLL channel for DRTIO satellite
2018-01-23 10:13:10 +08:00
626075cbc1
gtp_7series: simplify TX clocking
2018-01-23 09:49:23 +08:00
401e57d41c
gtp_7series: fix nchannels assert
2018-01-23 01:28:01 +08:00
aa62e91487
kasli: add DRTIO targets (no firmware)
2018-01-23 01:27:40 +08:00
296ac35f5d
sayma_amc: SFP TX disable is active-high
2018-01-23 00:32:09 +08:00
77192256ea
kc705: style
2018-01-23 00:02:35 +08:00
ab7c49d6d0
sayma_amc: raise error on invalid variant
2018-01-23 00:02:16 +08:00
c1ac3b66b1
sayma_rtm: fix 8fe463d4a
2018-01-23 00:01:45 +08:00
53facfef13
sayma: build fixes
2018-01-22 18:33:22 +08:00
25f3feeda8
refactor targets
2018-01-22 18:25:10 +08:00
5198c224a2
sayma,kasli: use new pin names
2018-01-22 11:51:07 +08:00
Florent Kermarrec
8fe463d4a0
sayma_rtm: add UART loopback to easily know if rtm fpga is alive
2018-01-20 06:04:34 +01:00
Florent Kermarrec
74ce7319d3
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
2018-01-20 06:04:18 +01:00
Florent Kermarrec
d27727968c
add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
2018-01-19 12:17:54 +01:00
cdbf95d46a
kasli: fix permissions
2018-01-19 18:31:20 +08:00
8ec33ae7bd
kasli: feed EEM clock fan-out from SI5324
2018-01-17 17:27:59 +01:00
ed3e3b2791
sayma_amc: clarify --with-sawg help
2018-01-17 12:10:30 +01:00
Florent Kermarrec
f54b27b79c
sayma_amc: prepare for jesd subclass 1
2018-01-17 11:49:36 +01:00
Florent Kermarrec
f73c3e5944
gateware/test/serwb: update and cleanup test (v2...)
2018-01-16 20:06:43 +01:00
7405006668
sayma: rtio clock is jesd fabric clock
2018-01-16 18:19:04 +01:00
whitequark
247167d34a
Revert "gateware/test/serwb: update and cleanup tests"
...
This reverts commit 5b03cc2fae
2018-01-16 08:21:26 +00:00
whitequark
444b901dbe
sayma: add RTM configuration port.
2018-01-16 07:28:00 +00:00
Florent Kermarrec
5b03cc2fae
gateware/test/serwb: update and cleanup tests
2018-01-15 21:53:40 +01:00
whitequark
6891141fa6
artiq_flash: add sayma support.
2018-01-15 11:43:29 +00:00
529033e016
kernel_cpu: disable PCU
...
* contributes to long timing paths on artix 7 (kasli)
* currently only used for testing and debugging
2018-01-12 12:03:50 +00:00
ac3c3871d0
kasli: s/extensions/variant/g
2018-01-12 12:29:42 +01:00
7c82fcf41a
targets: avoid passing cpu_type around unnecessarily
2018-01-11 11:21:55 +08:00
6d58c4390b
Merge branch 'sed-merge'
2018-01-10 13:14:39 +08:00
04b2fd3e13
sayma: fix AD9154NoSAWG ramp clock domain
2018-01-10 12:11:33 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
Florent Kermarrec
2009734b3c
serwb/phy: get 625Mbps linerate working, increase timeout
2018-01-09 18:54:52 +01:00
Florent Kermarrec
9c6a7f7509
serwb/kusphy: use same serwb_serdes_5x reset than s7phy
2018-01-09 18:54:05 +01:00
8813aee6b1
targets: add kasli [wip, untested]
2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8
gateware/targets: enable serwb scrambling on sayma amc & rtm
2018-01-03 17:34:46 +01:00
Florent Kermarrec
907af25a69
gateware/serwb: add scrambling, reduce cdc fifo depth
2018-01-03 17:34:03 +01:00
Florent Kermarrec
7f4756a869
gateware/serwb: cleanup packet
2018-01-03 17:30:12 +01:00
c2be820e9a
kc705_dds: make ext_clkout 100 MHz
2018-01-02 19:58:47 +01:00
43686f324b
kc705_dds: fix HPC voltages
...
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V
* the direction control register on HPC (FMC-DIO to VHDCI)
was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
and hope for the best.
2018-01-02 13:41:07 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
53969d3686
kc705_dds: add urukul on vhdci extension definition
2018-01-02 13:20:47 +01:00
2f8e6c7462
spi: add diff_term, save power on outputs
2018-01-02 13:20:47 +01:00
6d20b71dde
ttl_serdes_7series: refactor IOSERDES
2018-01-02 13:20:47 +01:00
745e695b09
sayma: output a ramp in the absence of SAWG channels
2017-12-31 12:18:53 +01:00
whitequark
a371b25525
bootloader: allow using without Ethernet.
2017-12-31 09:21:28 +00:00
6e0288e568
drtio: fix GTH CPLL reset
2017-12-30 12:14:36 +08:00
379d29561b
sayma: plausibility assertion on sawg data stream
2017-12-29 19:15:40 +01:00
37f9c0b10c
spi: register clk
...
following m-labs/misoc#65
1dc68b0d0b
2017-12-28 16:50:22 +01:00
whitequark
acd13837ff
firmware: implement the new bootloader.
2017-12-28 13:18:51 +00:00
8153cfa88f
drtio/gth: add probes on {tx,rx}_init.done
2017-12-28 16:49:08 +08:00
c086149782
drtio/gth: use async microscope probes
2017-12-28 16:37:40 +08:00
whitequark
d94db1de5d
Revert accidentally committed parts of 1b9b5602.
2017-12-28 08:23:34 +00:00
whitequark
1b9b560242
firmware: use libbuild_misoc in libdrtioaux. NFC.
2017-12-28 08:20:23 +00:00
6801921fc0
drtio: instrument GTH transceiver
2017-12-28 15:03:14 +08:00
70b7f28ad3
drtio: drive SFP TX disable pins
2017-12-23 22:58:51 +08:00
f8c8f3fe26
drtio: fix GTH clock domains
2017-12-23 07:21:44 +08:00
1af21c0b29
drtio: integrate GTH transceiver for Sayma
2017-12-23 01:19:59 +08:00
c57b66497c
drtio: refactor/simplify GTH, use migen
2017-12-23 01:19:44 +08:00
77897228ca
drtio: add GTH transceiver code from Florent (197c79d47)
2017-12-22 18:01:28 +08:00
ebdbaaad32
drtio: remove KC705/GTX support
2017-12-22 17:51:42 +08:00
0681d472c7
conda: fix sayma_rtm_csr.csv location for Sayma AMC
2017-12-22 17:14:10 +08:00
44959144d8
conda: add Sayma AMC standalone board package
2017-12-22 16:44:04 +08:00
Florent Kermarrec
86825a852c
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
2017-12-21 23:52:44 +01:00
a6ffe9f38d
drtio: add Sayma top-level designs
2017-12-21 23:08:56 +08:00
4fbc8772a5
sayma: allocate all user LEDs to RTIO, make one TTL SMA input
2017-12-21 19:27:38 +08:00
a23251276d
Revert "sayma: set up Si5324 for RGMII clock rerouting"
...
This reverts commit 2b01aa22b6
2017-12-21 14:42:15 +08:00
2b01aa22b6
sayma: set up Si5324 for RGMII clock rerouting
2017-12-17 00:25:33 +08:00
b6199bb35b
sayma: style
2017-12-15 19:45:51 +08:00
649b60ea29
targets/kc705_drtio: remove DAC FMC card support
2017-12-15 17:32:25 +08:00
341e809859
targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator
2017-12-15 13:08:35 +08:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
5e251cd85c
sayma_amc: remove redundant bitstream options
...
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
2017-12-13 14:39:32 +01:00
a9d0f253a5
sayma_amc: set bitstream and config parameters
...
* slow down CCLK rate as there is additional loading
on the signals
* single bit SPI for now until we know that quad SPI
works
* set up
https://github.com/m-labs/artiq/issues/847
2017-12-13 21:21:52 +08:00
whitequark
1c25f7ef52
gateware: make software builds spew less junk on the console.
...
[ci skip]
2017-12-04 14:19:35 +00:00
bb3d6ef84a
sayma: remove ad9154 from mem_map
...
Address is autogenerated by CSR system.
2017-11-29 18:17:25 +08:00
ecfe2e40ee
sayma_amc_standalone: rtio channels for both sawg groups
2017-11-19 18:32:42 +01:00
d1a7c1c3a1
sayma_amc_standalone: connect sawg to jesd again
2017-11-19 14:36:20 +01:00
Florent Kermarrec
dfdd2dd9e6
gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb
2017-11-19 09:01:20 +01:00
Florent Kermarrec
cd83b71d92
gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping
2017-11-18 18:10:28 +01:00
Florent Kermarrec
f003566e52
serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...
...
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
2017-11-18 18:01:46 +01:00
Florent Kermarrec
1b976bfa4d
gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x
2017-11-18 17:57:11 +01:00
Florent Kermarrec
464b24a608
gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints.
2017-11-10 10:48:32 +01:00
Florent Kermarrec
278c739d30
gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints
2017-11-10 10:39:47 +01:00
Florent Kermarrec
48bfaec8d3
gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8
2017-11-10 10:37:08 +01:00
Florent Kermarrec
59be095512
gateware/serwb/kusphy: use locally inverted clk_b on iserdese3
2017-11-10 10:35:48 +01:00
Florent Kermarrec
db82b11f29
gateware/serwb/core: cleanup and increase fifo depth
2017-11-10 10:33:39 +01:00
Florent Kermarrec
76ddb063cf
gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation)
2017-11-06 12:08:28 +01:00
Florent Kermarrec
5bd1e43ced
gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender
2017-11-03 12:15:14 +01:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
d5b5076f67
gateware/ad5360_monitor: fix SPI data decoding
2017-10-26 11:58:59 +08:00
412548a86c
gateware: add AD5360 monitor (untested)
2017-10-23 20:09:28 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
4fa823b62a
gateware: add support for SPI-over-LVDS
2017-10-23 15:04:01 +08:00
893be82ad1
rtio/dma: raise underflow in test
2017-10-09 10:22:58 +08:00
a9c9d5779d
rtio/dma: add full-stack test with connection to RTIO core
2017-10-08 22:38:02 +08:00
5f083f21a4
rtio/dma: fix signal width
2017-10-08 22:37:46 +08:00
c7de233208
Merge Sayma SAWG changes (untested)
...
See #798
* sinara:
conda: bump migen
sayma_amc: SAWG (untested)
sayma_rtm: make build dir
conda: jesd204b 0.4
2017-09-29 21:01:02 +02:00
b4c52c34f7
Merge branch 'sinara'
2017-09-30 01:11:16 +08:00
6c049ad40c
rtio: report channel numbers in asynchronous errors
2017-09-29 16:32:57 +08:00
5437f0e3e3
rtio: make sequence errors consistently asychronous
2017-09-29 14:40:06 +08:00
5e3cc83842
sayma_amc: SAWG (untested)
2017-09-27 18:44:35 +02:00
2604806512
sayma_rtm: make build dir
2017-09-27 18:35:46 +02:00
73043c3464
drtio: disable SED lane spread
...
Doesn't improve things as the buffer space would still be determined
by the full FIFO, and adds unnecessary logic.
2017-09-26 16:46:09 +08:00
d7ef07a0c2
rtio/sed: document architecture
2017-09-26 16:44:23 +08:00
e6f0ce3aba
rtio/sed: test latency compensation
2017-09-26 16:11:21 +08:00
9905b8723b
rtio/sed: support negative latency compensation
2017-09-26 16:11:08 +08:00
f079ac6af6
rtio/sed: disable wait in TestLaneDistributor.test_regular
2017-09-26 16:10:52 +08:00
4112e403de
rtio/sed: latency compensation
2017-09-26 15:09:07 +08:00
e430d04d3f
drtio: remove obsolete import
2017-09-24 12:49:21 +08:00
20d79c930c
drtio: use SED and input collector
2017-09-24 12:23:47 +08:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
5cf0693758
rtio: use BlindTransfer to report collision and busy errors to sys domain
2017-09-21 22:31:56 +08:00
d74a7d272e
rtio: fix/cleanup parameters
2017-09-21 15:59:48 +08:00
07d3f87c51
rtio/sed: min_space → buffer_space
2017-09-21 14:36:13 +08:00
d8aa75b742
rtio/sed: add minimum buffer space reporting
2017-09-20 11:27:57 +08:00
63e39dec94
style
2017-09-20 11:26:12 +08:00
9ccd95e10d
drtio: remove spurious signals
2017-09-19 20:48:12 +08:00
7249f151a5
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:48:12 +08:00
171a2d19a0
drtio: remove spurious signals
2017-09-19 20:47:37 +08:00
1ff10785dc
targets/kc705_drtio_satellite: add missing shebang line
2017-09-19 20:46:16 +08:00
ddcd6065e8
rtio: drive InputCollector.coarse_timestamp
2017-09-19 17:46:38 +08:00
ff8e17ab89
rtio: use input collector module
2017-09-19 15:53:35 +08:00
4dc80e3d05
rtio: add missing import
2017-09-19 15:53:23 +08:00
06a0707c00
rtio: add simulation unit test for input collector
2017-09-19 15:30:44 +08:00
d37577a8a1
rtio: add input collector module
2017-09-19 15:30:30 +08:00
6dc9cad2c9
rtio: add explanation about cri.counter
2017-09-19 12:05:12 +08:00
81d6317053
rtio/sed: take global fine TS width
2017-09-18 11:30:49 +08:00
65baca8c57
rtio: clean up error-prone rtlink.get_or_zero()
2017-09-17 16:11:36 +08:00
0824e0aeae
gateware/targets: remove deprecated ofifo_depth parameter
2017-09-16 17:04:11 +08:00
e2c1d4f3d5
rtio/sed: trigger collision error on non-data replace
2017-09-16 17:01:23 +08:00
0e25154e25
rtio/sed: quash writes to LogChannel
2017-09-16 15:19:30 +08:00
1cfe90b1d9
rtio/sed/Gates: fix fine_ts_width computation
2017-09-16 15:09:21 +08:00
30e7765a2e
drtio: add missing import
2017-09-16 14:36:27 +08:00
a3bb6c167c
rtio: use SED
2017-09-16 14:13:42 +08:00
131f5e4a3b
rtio/sed/LaneDistributor: fix CRI address
2017-09-16 14:13:01 +08:00
25c644c663
rtio/sed: add top-level core unit test
2017-09-16 14:05:08 +08:00
a155a481b1
rtio/sed: add top-level core
2017-09-16 14:04:56 +08:00
92c63ce2e4
rtio/sed: rename fifos/gates, refactor tsc
2017-09-16 14:03:48 +08:00
ac52c7c818
rtio/sed/LaneDistributor: style
2017-09-16 14:02:37 +08:00
7b299ba583
rtio/sed: remove obsolete ofifo_depth from test_output_driver
2017-09-16 14:01:19 +08:00
6b7a1893c7
rtio/sed/OutputDriver: support channels with different fine timestamp widths
2017-09-16 10:53:30 +08:00
f39ee7ad62
rtio/sed: fix seqn_width
2017-09-16 10:52:37 +08:00
064503f224
rtio/sed/LaneDistributor: support specifying existing CRI
2017-09-16 10:52:13 +08:00
1cb05f3ed5
rtio/sed/LaneDistributor: persist underflow/sequence error until next write
2017-09-16 10:51:44 +08:00
3c922463a0
style
2017-09-15 15:36:46 +08:00
8e5ab90129
rtio/sed: add FIFO wrapper
2017-09-15 15:36:34 +08:00
490c9815a2
rtio/sed: add TSC/gate (untested)
2017-09-14 19:53:21 +08:00
181cb42ba8
rtio/sed: centralize all layouts in one file
2017-09-14 19:52:31 +08:00
1b61442bc3
rtio/sed: fix lane spreading and enable by default
2017-09-13 22:48:10 +08:00
8cfe2ec53a
rtio/sed: fix sequence number width computation
2017-09-13 22:11:41 +08:00
a92a955d1e
rtio/sed: use __all__
2017-09-13 18:17:22 +08:00
feec6298a5
rtio/sed: add lane distributor simulation unittest
2017-09-13 18:00:16 +08:00
c74abccfd5
rtio/sed: lane distributor fixes
2017-09-13 17:50:06 +08:00
bdd96084c5
rtio/sed: add lane distributor (untested)
2017-09-13 00:07:26 +08:00
faf54127ac
rtio/sed: remove VCD fine in unittest
2017-09-11 23:07:09 +08:00
a2b7894134
rtio/sed: add output driver simulation unittest
2017-09-11 23:05:10 +08:00
00ff3f5b0d
rtio/sed: fix output driver busy output
2017-09-11 23:04:52 +08:00
64d9381c36
rtio/sed: remove uneeded yield in test_sed_output_network
2017-09-11 23:02:56 +08:00
666bc600a2
rtio/sed: add output driver (untested)
2017-09-11 11:10:28 +08:00
1d2ebbe60f
rtio/sed: make ON payload layout configurable, add latency function
2017-09-11 09:06:40 +08:00
527b403bb1
rtio/sed: add output network simulation unittest
2017-09-10 23:41:20 +08:00
c5d6a2ba1a
rtio/sed: more output network fixes
2017-09-10 23:41:04 +08:00
96505a1cd9
rtio/sed: output network fixes
2017-09-10 23:23:10 +08:00
5646e19dc3
rtio/sed: add output network (untested)
2017-09-10 14:38:43 +08:00
Florent Kermarrec
2091c7696a
artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode
2017-09-06 09:18:12 +02:00
9edff2c520
remote_csr: interpret length as CSR size, not number of bus words
2017-08-31 13:34:48 +08:00
0a5904bbaa
firmware: support for multiple JESD DACs
2017-08-31 13:05:48 +08:00
a4144a07c4
sayma_amc: add converter SPI config defines
2017-08-31 13:04:38 +08:00
bacf8a1614
style
2017-08-31 12:52:09 +08:00
ad0a940e2d
sayma_rtm: hook up DAC SPI
2017-08-31 11:48:54 +08:00
f765dc50de
sayma_rtm: do not keep DACs in reset
2017-08-31 11:44:33 +08:00
a67659338d
sayma: clean up serwb comments
2017-08-31 11:42:01 +08:00
Florent Kermarrec
660f9856ec
gateware/serwb: add test for phy initialization
2017-08-30 17:59:10 +02:00
Florent Kermarrec
9650233007
gateware/serwb: change serdes clock domain to serwb_serdes
2017-08-30 15:44:44 +02:00
Florent Kermarrec
32ca51faee
gateware/targets/sayma_amc_standalone/rtm: use new serwb modules
2017-08-30 15:25:20 +02:00
Florent Kermarrec
41d57d64f6
gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window
2017-08-30 14:40:11 +02:00
Florent Kermarrec
9ba50098a8
gateware/test/serwb: use unittest for in test_etherbone
2017-08-29 17:31:01 +02:00
Florent Kermarrec
7d7f6be7ce
gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction
2017-08-29 16:41:29 +02:00
Florent Kermarrec
60ad36e7d6
gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready
2017-08-29 13:43:26 +02:00
Florent Kermarrec
89558e2653
gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
...
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
2017-08-29 13:38:52 +02:00
26a11a296c
sayma_rtm: drive DAC control signals
2017-08-26 16:57:02 -07:00
d609c67cbd
sayma_rtm: set clock mux pins
2017-08-26 16:48:10 -07:00
9194402ea5
sayma_rtm: expose HMC SPI bus
2017-08-26 16:31:31 -07:00
dbc12540da
sayma_amc: register RTM CSR regions from CSV
2017-08-26 14:48:11 -07:00
54c75d3274
sayma_rtm: use CSR infrastructure, generate CSR CSV
2017-08-23 17:19:53 -04:00
668450db26
sayma_amc: add serwb
2017-08-21 18:11:29 -04:00
0459a70cf6
sayma_amc: cleanup, fix RTM UART forwarding
2017-08-21 16:49:42 -04:00
1f2b373d09
sayma_rtm: remove unnecessary serwb_control
2017-08-21 16:37:13 -04:00
bfea297279
targets: add Sayma RTM
2017-08-21 15:58:01 -04:00
53c7f92fdc
serwb: add __init__.py and expose submodules
2017-08-21 15:57:43 -04:00
dac3a78b75
serwb: style, use migen, fix imports
2017-08-21 12:35:59 -04:00
Florent Kermarrec
da90a0fa12
Add test for Etherbone
...
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
2017-08-21 12:31:49 -04:00
Florent Kermarrec
44dc76e42e
Add serial Wishbone bridge
...
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
2017-08-21 12:22:05 -04:00
d6b624dfbe
sayma_amc: connect RTM serial and second serial
2017-08-20 19:01:55 -04:00
bee4902323
add Sayma AMC standalone target
2017-08-20 11:47:45 -04:00
1dab7df846
kc705_sma_spi: fix permissions
2017-08-20 10:54:24 -04:00
df4f38a1e4
kc705: add pullup on SD card MISO
2017-07-24 22:26:16 +08:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
...
This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
7b130a2c32
sawg: confirm smooth(order=3)
2017-07-07 11:36:03 +02:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
...
This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
...
closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
...
closes #771
2017-07-04 16:50:06 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
...
closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
...
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f
sawg: use pipeline reset
2017-06-28 19:09:39 +02:00
6418205906
dsp.fir: use pipelin-reset
2017-06-28 19:09:21 +02:00
07f5e99140
dsp/sat_add: works after previous changes
2017-06-22 18:24:22 +02:00
f78d5a87e9
dsp/test: skip and fix sat_add
2017-06-22 18:01:31 +02:00
47928a2c0d
sawg: disable limiter
...
temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5
dsp/sat_add: make width mandatory
2017-06-22 17:28:39 +02:00
9b940aa876
dsp/sat_add: spell out logic more
2017-06-22 16:55:13 +02:00
d0cf0f2b87
sawg/limiter: make signed signals explicitly
2017-06-22 13:44:36 +02:00
694f8d784c
dsp/tools: unittest sat_add
2017-06-22 11:29:56 +02:00
bd1438d28e
sawg: wrap limits init values
2017-06-22 10:26:29 +02:00
cccd01e81e
sawg: cleanup sat_add logic
2017-06-22 10:26:29 +02:00
5f6e665158
test/sawg: patch delay_mu
2017-06-22 10:26:29 +02:00
570f2cc1ff
dsp/tools/SatAdd: fix reuse of clipped signal
2017-06-22 10:26:29 +02:00
4b3aad2563
sawg: clean up Config
...
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
ff0da2c9fc
sawg: stage code for y-data exchange on channels
2017-06-22 10:26:29 +02:00
b6569df02f
dsp/tools: clean up SatAddMixin logic
2017-06-22 10:26:29 +02:00
74cf074538
drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times
2017-06-21 17:01:52 +08:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
e19bfd4781
test_sawg_fe: add ref_multiplier to simulated core
2017-06-16 19:45:24 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
3f37870e25
sawg: register pre-hbf adder
2017-06-13 18:15:44 +02:00
e229edd5d5
sawg: add register after hbf for timing
2017-06-12 23:08:27 +02:00
315338fca9
test/sawg: test HBF overshoot, fix sim patching
2017-06-12 20:35:47 +02:00
9a8a7b9102
sawg: handle clipping interpolator
...
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC
This leaves a factor of two headroom for the sum of the following
effects:
* HBF overshoot (~15 % of the step)
* A1/A2 DDS sum
While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?
closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc
Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
...
This reverts commit 6ac9d0c41e
2017-06-12 20:07:25 +02:00
332bcc7f3b
fir: check widths
2017-06-12 20:07:23 +02:00
39a1dcbb3d
test/fir: look at overshoot behavior
2017-06-12 20:06:07 +02:00
6ac9d0c41e
fir/ParallelHBFUpsampler: add headroom (gain=2)
...
This addresses part of #743
2017-06-12 18:59:45 +02:00
bfc224d4ba
phaser: adjust to new jesd
2017-05-22 19:59:53 +02:00
679060af1d
phaser: enable dma
2017-05-22 19:32:34 +02:00
4901cb9a8a
sawg: fix clr width
2017-05-22 17:46:55 +02:00
253ee950f6
sawg: fix config channel addr
2017-05-22 17:45:14 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
170d2886fd
Merge branch 'pdq'
...
* pdq:
pdq: documentation
pdq2 -> pdq
pdq2: use 16 bit data, buffered read_mem()
spi: style
pdq2: mem_read
pdq2: align subsequent writes to end
sma_spi: undo cri_con
pdq2: memory write, kernel_invariants
sma_spi: cri/cd changes
sma_spi: LVCMOS25
coredevice.spi: kernel invariants and style
sma_spi: free up user_sma pins
sma_spi: add demo target with SPI on four SMA
pdq2: memory write
pdq2: crc/frame register accessors
doc: pdq2 spi backend
pdq2: config writes
2017-05-12 11:46:45 +02:00
Florent Kermarrec
79c339d4ac
gateware/targets/phaser: jesd core now handles jsync completely
2017-04-26 22:25:08 +02:00
Florent Kermarrec
0546affd4c
gateware/target/phaser: jesd start signal renamed to jsync
2017-04-26 12:27:40 +02:00
ed8edf318d
sma_spi: undo cri_con
2017-04-08 17:19:35 +02:00
16b7f8f50c
sma_spi: cri/cd changes
2017-04-08 17:16:19 +02:00
1e6e81a19e
sma_spi: LVCMOS25
2017-04-08 17:16:19 +02:00
555b3c38c1
sma_spi: free up user_sma pins
2017-04-08 17:16:19 +02:00
2c7c6143ab
sma_spi: add demo target with SPI on four SMA
2017-04-08 17:16:19 +02:00
c2667debf8
drtio: test replace in RTL simulation
2017-04-06 16:33:59 +08:00
729e7b52f0
drtio: collision/replace fixes
2017-04-06 16:33:49 +08:00
83d87b5805
drtio: remove outdated comment
2017-04-06 12:45:10 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
674bf82f3a
gateware: add cri_con CSRs to all DMA-capable targets
2017-04-06 01:14:09 +08:00
5e3aef45dc
drtio: support collision/replace + detect sequence errors at satellite
2017-04-06 01:06:56 +08:00
whitequark
17b5388259
gateware: remove one stray CRI arbiter remnant.
2017-04-05 16:38:56 +00:00
whitequark
464202d0aa
gateware: connect CRI switch to kernel CPU.
2017-04-05 16:10:53 +00:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
8c414cebc7
drtio: report busy errors
2017-04-03 00:11:08 +08:00
008678b741
drtio: add infrastructure for reporting busy/collision errors
2017-04-02 23:45:55 +08:00
0a687b7902
drtio: report satellite errors through firmware
2017-04-01 12:18:00 +08:00
28211e0b32
gateware: reset RTIO DMA core when kernel CPU is reset
2017-03-31 15:35:28 +08:00
200c499114
test: change base address in DMA simulation testbench
2017-03-31 13:17:00 +08:00
ea3af1e20e
drtio: remove obsolete CSR accesses from test
2017-03-27 16:44:22 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9
gateware: reverse bytes of SDRAM word, not bits.
2017-03-17 11:16:46 +00:00
whitequark
6b63322106
gateware: reverse SDRAM words in RTIO DMA engine.
2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb
gateware: work around ISE/Vivado bugs with very wide shifts.
2017-03-17 07:29:28 +00:00
whitequark
4beda73217
firmware: don't build libdyld through misoc.
2017-03-14 08:33:31 +00:00
a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
13ae1d1a38
drtio: input unittest
2017-03-14 14:14:55 +08:00
56fd9b3b4b
drtio: input fixes
2017-03-14 14:14:43 +08:00
95ede18809
drtio: support PHY latency compensation
2017-03-14 00:01:38 +08:00
497c795d8c
drtio: input support (untested)
2017-03-13 23:54:44 +08:00
d1b9f9d737
drtio: rt_packets → rt_packet
2017-03-13 00:10:07 +08:00
6b7c781ff2
drtio: introduce 'standard request' interface in RT packet layer
2017-03-13 00:08:03 +08:00
2b8729f326
drtio: clear any read request on satellite reset
2017-03-13 00:00:38 +08:00
1e47e638bb
drtio: implement inputs in RTPacketSatellite, reorganize code
2017-03-07 00:46:59 +08:00
1e6a33b586
rtio: handle input timeout in gateware
...
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
2017-03-03 17:37:47 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
7d6ebabc1b
reorganize core device communication code
2017-02-27 18:37:30 +08:00
f017d1771f
gateware: remove unused configs in targets (not needed with new moninj)
2017-02-25 12:14:56 +08:00
360be0098f
drtio: map local RTIO core on lower channels
2017-02-24 18:15:27 +08:00
b455ea447d
gateware: add moninj to drtio targets
2017-02-21 21:54:47 +08:00
c66efc0279
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
c022b53578
kernel_cpu: enable perf counters
2017-02-18 14:09:12 +01:00
935799dfb7
drtio: fix satellite transceiver clocking
2017-02-04 19:18:35 +08:00
whitequark
b9cbedceb1
firmware: migrate last vestiges of the old runtime build system.
2017-02-03 12:59:35 +00:00
a8ecbd6041
firmware: do not attempt to build Si5324 code when gateware does not support it
2017-02-03 12:27:13 +08:00
d181989de9
drtio: reset Si5324 at each boot
2017-02-03 12:00:58 +08:00
b3697f951a
drtio: forward clocks to SMA connectors for debugging
2017-02-03 12:00:36 +08:00
aafefee7f5
targets: make number of ethmac slots consistent
2017-02-02 23:02:51 +08:00
whitequark
44a9a79f96
firmware: port allocator to Rust.
2017-02-02 10:55:35 +00:00
f512ea42dc
drtio: initialize si5324 in firmware
2017-02-02 18:11:24 +08:00
whitequark
b95db4fa4e
Use four ethmac buffers instead of two.
...
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
2017-01-30 07:42:27 +00:00
9800acea92
drtio: program Si5324 for 150MHz in 3G config
2017-01-30 14:50:12 +08:00
7daab07a29
drtio: fix syntax/import
2017-01-30 13:01:45 +08:00
d8e9949266
drtio: initialize AD9516 clock chip
2017-01-30 11:06:45 +08:00
f6024b6c9a
drtio: fix ad9154 extension registration
2017-01-30 10:59:22 +08:00
43aad0914e
python3.5 -> python3
...
Many things also work with Python 3.6.
2017-01-30 09:24:43 +08:00
657afd770e
artiq/test/gateware -> artiq/gateware/test
...
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
2017-01-30 09:00:55 +08:00
94b0783897
drtio: remove support for transceiver SMAs
...
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
2017-01-27 23:33:50 +08:00
whitequark
de17908b38
Revert "Globally update UART baudrate to 921600."
...
This reverts commit b29e2d5bfe
2017-01-25 00:31:28 +00:00
whitequark
b29e2d5bfe
Globally update UART baudrate to 921600.
2017-01-24 22:25:58 +00:00
whitequark
527b1e986c
firmware: integrate smoltcp instead of lwip.
2017-01-23 13:59:34 +00:00
28a41a2f60
gateware: fix aeb1ba847
2017-01-18 17:11:02 -06:00
2a7a8f91ca
gateware: fix import
2017-01-18 16:51:30 -06:00
ce31ffddb0
firmware: add satellite manager
...
The code duplication with the runtime should be cleaned up later.
2017-01-18 16:50:32 -06:00
b40953800a
gateware: soc -> amp.soc
2017-01-18 15:28:14 -06:00
aeb1ba8471
gateware: use default MiSoC timer
2017-01-18 15:22:33 -06:00
b8d89d56b1
drtio: add GenericRXSynchronizer
2017-01-15 13:44:43 -06:00
0edffb54c2
drtio: fix packet truncation detection in RTPacketSatellite
2017-01-13 09:29:22 -06:00
6805feb494
drtio: report truncated packets
2017-01-12 23:44:45 -06:00
7c699e2f80
drtio: add FIFO space request count debug API
2017-01-11 13:48:14 -06:00
c25186fae1
drtio: print packet error descriptions in log
2017-01-10 18:03:01 -06:00
98598df78e
rtio: keep retrying on get FIFO space timeout
2017-01-10 16:12:32 -06:00
e624f45369
drtio: remove FIFO empty local detection optimization
...
It optimizes a marginal case, it is difficult to get right
(need to know the size of the FIFO for each channel), and
it adds complexity and potential bug sources.
2017-01-10 14:31:46 -06:00
f75fffcf96
drtio: fix satellite RX data corruption
2017-01-10 14:29:30 -06:00
fe53bab953
targets: kc705 -> kc705_dds
2017-01-05 18:40:56 +01:00
082fdaf450
move i2c to libboard, do bit-banging on comms CPU
2017-01-04 21:04:38 +01:00
86f6b391b7
ad9xxx -> ad9_dds
2017-01-04 11:34:52 +01:00
c08fc8aae9
firmware: support moninj without DDS. Closes #650
2017-01-04 11:26:02 +01:00
455250b3f9
remove DDS_AD9914 and DDS_ONEHOT_SEL
2017-01-03 22:04:25 +01:00
fbf5a4d4a2
Merge branch 'phaser2-rust-init'
2017-01-03 21:31:21 +01:00
9a80b8d533
spi: fix xfers with full data_width ( closes #615 )
...
misoc 15000af43611bbe8be13cb2b016e408f043202cd
2017-01-03 19:51:14 +01:00
7ff77bceac
move AD9616 and AD9154 initialization to firmware
2017-01-03 16:11:38 +01:00
417708af90
phaser: add note about DDS defines ( #650 )
2017-01-02 22:15:21 +01:00
f5f662200b
fir: streamline, optimize DSP extraction, left-align inputs
2016-12-20 21:39:51 +01:00
cfb66117af
fir: size hint for pre-adder
2016-12-20 17:58:06 +01:00
f310274e39
fir: cleanup halfgen4
2016-12-20 17:58:06 +01:00
6b998581cc
rtio: use same reset for counter_rtio whatever the interface delay is
2016-12-15 09:28:13 +08:00
115ea67860
fir: automatically use transposed topology
2016-12-14 19:16:07 +01:00
a451b675c9
Revert "fir: different adder layout"
...
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
2016-12-14 19:16:07 +01:00
93076b8efa
fir: different adder layout
2016-12-14 19:16:07 +01:00
61abd994e9
Revert "fir: force dsp48"
...
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
2016-12-14 19:16:07 +01:00
641d109786
fir: force dsp48
2016-12-14 19:16:07 +01:00
8381db279f
sawg: wire up all HBF outputs, latency compensation in phys, simplify
2016-12-14 19:16:07 +01:00
6cdb96c5e0
rtio: add support for latency compensation in phy
...
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
2016-12-14 19:16:07 +01:00
4c27029be0
sawg: fix limit regs
2016-12-14 19:16:07 +01:00
e9592105ce
drtio: fix aux controller clock domain mistakes
2016-12-14 10:16:45 +08:00
527757b471
kc705_drtio: use ad9154_fmc_ebz
2016-12-13 14:30:26 +08:00
3b5abae935
drtio: fix clock domain conflict
2016-12-13 14:19:49 +08:00
03d13d3811
phaser: dma/drtio changes
2016-12-12 17:46:36 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
4b61020b27
drtio: reset more local state
2016-12-12 18:48:10 +08:00
d99e64effd
drtio: clear any stale FIFO space reply
2016-12-12 18:02:56 +08:00
4c59c0fecf
Revert "drtio: order resets wrt writes"
...
This reverts commit 9a048c2b3a
2016-12-12 17:49:07 +08:00
8f747fa209
drtio: clear underflow and sequence error on reset
2016-12-12 17:39:14 +08:00
7196bc21c1
rtio: simplify error reset logic
...
Channel is always selected when reset is issued.
2016-12-12 17:35:10 +08:00
9a048c2b3a
drtio: order resets wrt writes
2016-12-12 17:18:07 +08:00
0a9f69a3ed
kc705_drtio_master: add missing rtio_core CSRs
2016-12-09 19:23:36 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
f6071a5812
sawg/hbf: tweak pipeline for timing
2016-12-08 17:00:53 +01:00
b7a308d33d
fir: register multiplier output
2016-12-08 17:00:39 +01:00
18e3f58c22
sawg: reduce coefficient width
2016-12-08 16:14:32 +01:00
598da09a93
sawg: fix latency
2016-12-08 15:53:35 +01:00
3eef6229cc
sawg: use ParallelHBFCascade to AA [WIP]
2016-12-08 15:32:57 +01:00
a629eb1665
fir: add ParallelHBFCascade
2016-12-08 15:30:26 +01:00
d303225249
fir: add ParallelFIR and test
2016-12-08 15:21:04 +01:00
7e0f3edca5
gateware/dsp: add FIR and test
2016-12-07 19:14:23 +01:00
4c3717932e
drtio: link layer debugging CSRs
2016-12-07 23:03:14 +08:00
b311830fc4
kc705: fix drtio_aux address conflict
2016-12-06 18:28:48 +08:00
4669d3f02f
kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller
2016-12-06 14:56:42 +08:00
f4b7d39a69
kc705_drtio_master: hook up auxiliary controller
2016-12-06 14:56:15 +08:00
f3c50a37ca
rtio: always read full DMA sequence
2016-12-06 01:05:47 +08:00
c413d95b49
rtio: fix DMA get_csrs
2016-12-05 18:12:09 +08:00
b677c69faf
rtio: fix handling of o_status in DMA
2016-12-05 18:01:48 +08:00
75ea13748a
rtio: fix DMA data MSB and stop signaling, self-checking unittest
2016-12-05 18:01:48 +08:00
a5834765d0
rtio: more DMA fixes, better stopping mechanism
2016-12-05 18:01:48 +08:00
30bce5ad35
rtio: DMA fixes
2016-12-05 18:01:48 +08:00
88ad054ab6
Merge branch 'drtio'
2016-12-03 23:25:17 +08:00
5d145ff912
drtio: add false paths between sys and transceiver clocks
2016-12-03 23:03:01 +08:00
4b97b9f8ce
drtio: add clock constraints
2016-12-03 22:17:29 +08:00
e747696aaa
Merge remote-tracking branch 'm-labs/phaser2' into phaser2
...
* m-labs/phaser2:
phaser: fix typo
2016-12-02 14:11:56 +01:00
cbf1004df3
gateware/phaser -> gateware/ad9154_fmc_ebz
2016-12-02 14:11:41 +01:00
6353f6d590
drtio: support different configurations and speeds
2016-12-02 17:22:22 +08:00
3cee269afe
phaser: fix typo
2016-12-02 11:06:45 +08:00
3931d8097b
rtio: fix DMA TimeOffset stream.connect
2016-12-01 16:43:46 +08:00
d4cb1eb998
kc705: integrate DMA
2016-12-01 16:31:00 +08:00
7c59688a12
rtio: simple DMA fixes
2016-12-01 16:30:48 +08:00
46dbc44c8f
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
6c97a97d8c
rtio: support single-master CRI arbiter
2016-12-01 16:30:11 +08:00
a318243083
rtio: CRI arbiter (untested)
2016-12-01 15:41:43 +08:00
cd3f68ba76
rtio: DMA core (untested)
2016-11-30 18:43:19 +08:00
d8b5eac856
sawg: style
2016-11-29 20:51:40 +01:00
27160f5912
phaser: make sysref input only for timing
2016-11-29 15:28:10 +01:00
cf342eca6e
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-29 10:44:27 +08:00
f4c6d6eb69
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-28 15:18:54 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
9fdd29ddae
drtio: connect KernelInitiator correctly
2016-11-28 14:36:18 +08:00
5460202220
drtio: typo
2016-11-28 14:35:21 +08:00
4e1b497742
drtio: typo
2016-11-28 14:34:58 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
046b8bfd33
drtio: fix transmit datapath with transceiver width > max packet width
2016-11-27 13:19:12 +08:00
0903964488
drtio: large data fixes
2016-11-27 02:12:50 +08:00
8090abef5d
drtio: large data support
2016-11-25 17:04:09 +08:00
55e37b41ec
phaser: use ttl_simple.Input for sync
2016-11-24 15:55:26 +01:00
8060652913
phaser: use Inout_8X
2016-11-24 15:21:03 +01:00
617650f3b2
phaser: extract target
2016-11-24 15:20:51 +01:00
1c84d1ee59
Merge branch 'master' into phaser2
...
* master:
rtio: support differential ttl
RELEASE_NOTES: int(a, width=b) removal, use int32/64
pc_rpc: use ProactorEventLoop on Windows (#627 )
2016-11-24 15:05:49 +01:00
95c885b580
rtio: support differential ttl
2016-11-24 15:04:12 +01:00
