470bce6214
coredevice: add AD9154 SPI access driver
2017-06-20 00:48:50 +08:00
a6d06824e7
fix indentation
2017-06-20 00:12:11 +08:00
8f2d85fc5b
add back ad9154_reg.py
2017-06-19 23:45:32 +08:00
c86029bca2
i2c: expose restart as syscall, add structure for I2C-over-DRTIO
2017-06-19 23:44:51 +08:00
268b7d8aaf
typo
2017-06-19 15:42:10 +08:00
09d198c7a1
test: add test for exception on non-existent I2C bus
2017-06-19 15:32:09 +08:00
d08bd58dff
versioneer: cut git hashes consistently ( #753 )
2017-06-19 15:31:48 +08:00
6c6bb67618
libboard: fix compiler warning on not(has_i2c)
2017-06-19 14:57:15 +08:00
5d63489080
i2c,spi: add busno error detection
2017-06-19 14:27:30 +08:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
8399f8893d
add kernel access to non-realtime SPI buses ( #740 )
2017-06-18 12:45:07 +08:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
8fea361412
firmware: always use 8 characters to abbreviate git commit hashes
2017-06-17 14:43:50 +08:00
e19bfd4781
test_sawg_fe: add ref_multiplier to simulated core
2017-06-16 19:45:24 +02:00
b5772f478a
sawg: add channel reset ( closes #751 )
2017-06-16 19:31:57 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
fecc42fd0c
sawg/phaser: expand documentation ( closes #750 )
2017-06-14 11:49:52 +02:00
858c1be381
sawg: expand documentation
2017-06-13 18:51:48 +02:00
3f37870e25
sawg: register pre-hbf adder
2017-06-13 18:15:44 +02:00
e229edd5d5
sawg: add register after hbf for timing
2017-06-12 23:08:27 +02:00
315338fca9
test/sawg: test HBF overshoot, fix sim patching
2017-06-12 20:35:47 +02:00
9a8a7b9102
sawg: handle clipping interpolator
...
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC
This leaves a factor of two headroom for the sum of the following
effects:
* HBF overshoot (~15 % of the step)
* A1/A2 DDS sum
While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?
closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc
Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
...
This reverts commit 6ac9d0c41e
2017-06-12 20:07:25 +02:00
332bcc7f3b
fir: check widths
2017-06-12 20:07:23 +02:00
39a1dcbb3d
test/fir: look at overshoot behavior
2017-06-12 20:06:07 +02:00
6ac9d0c41e
fir/ParallelHBFUpsampler: add headroom (gain=2)
...
This addresses part of #743
2017-06-12 18:59:45 +02:00
566ff73dff
pdq: unify spi-PDQ and usb-PDQ protocols
2017-06-10 15:03:25 +02:00
6c54c0f834
sawg: update example
2017-06-10 11:52:48 +02:00
d8aee931ba
sawg: extend phase mode docs
2017-06-09 12:26:49 +02:00
whitequark
f7254dd3ce
compiler.validators.constness: take AugAssign into account.
2017-06-09 07:31:08 +00:00
whitequark
ad2ee714c2
compiler: do not permit iterating str values.
...
This currently breaks badly on UTF-8, and doesn't even return
a value of a correct type.
2017-06-09 07:29:31 +00:00
whitequark
4e7493843a
compiler: Constness is a validator, not analysis.
2017-06-09 07:29:31 +00:00
whitequark
5d841d08e9
compiler: do not permit mutation of bytes values ( #714 ).
2017-06-09 07:29:28 +00:00
whitequark
284382b1f5
compiler: add support for bytearray values in RPC ( #714 ).
2017-06-09 07:15:25 +00:00
whitequark
9ed4e9c1cd
compiler: add support for printing of bytearray values ( #714 ).
2017-06-09 07:15:25 +00:00
whitequark
e9564b15c8
compiler: add support for bytearray type ( #714 ).
2017-06-09 07:15:24 +00:00
whitequark
5b4fde30a8
compiler: unbreak subscripts for bytes values ( #714 ).
2017-06-09 07:10:48 +00:00
whitequark
66a683f583
compiler: add support for bytes values in RPC ( #714 ).
2017-06-09 07:10:48 +00:00
whitequark
778e7dc2ab
compiler: add support for concatenating bytes values ( #714 ).
2017-06-09 07:10:48 +00:00
whitequark
7b2da5294f
compiler: add support for printing of bytes values ( #714 ).
2017-06-09 07:10:48 +00:00
whitequark
dba4e1a28b
compiler: add support for bytes type and b"x" literals ( #714 ).
2017-06-09 07:10:48 +00:00
whitequark
d0e92067c3
ksupport: fix UB.
2017-06-09 06:18:20 +00:00
91ad2bc600
sawg: add note about disabled q-exchange
2017-06-07 09:13:01 +02:00
94273e9455
sawg: add non-mu methods for limiter
2017-06-07 09:12:36 +02:00
ebb4660207
coredevice: compare software and gateware versions strictly
2017-06-07 02:11:54 +08:00
f3c7a7de3b
phaser: remove non-functional SPI examples
...
Those will be reimplemented after we have converter SPI access, but this will not be part of the 3.0 release.
2017-06-06 17:37:13 +08:00
ab493a860d
coredevice: fix socket resource leak
2017-06-05 15:45:40 +08:00
bea7a47349
coredevice: compare gateware and software versions on release numbers only. Closes #738
2017-06-05 13:52:24 +08:00
9c973793df
update versioneer
2017-06-05 13:27:26 +08:00
92307d1f9c
fix some missing pdq2→pdq renames
2017-06-03 18:35:36 +08:00
2458da1ade
pdq: get new host driver, adapt
2017-05-31 00:20:10 +02:00
2895448477
sawg: link Spline in docs
2017-05-23 10:33:04 +02:00
52625d57f0
sawg: explain DUC
2017-05-23 10:28:23 +02:00
bfc224d4ba
phaser: adjust to new jesd
2017-05-22 19:59:53 +02:00
679060af1d
phaser: enable dma
2017-05-22 19:32:34 +02:00
06721c19c4
sawg: work around bool->int
2017-05-22 18:50:58 +02:00
1562f79101
sawg: expose config channel
2017-05-22 18:27:42 +02:00
4901cb9a8a
sawg: fix clr width
2017-05-22 17:46:55 +02:00
253ee950f6
sawg: fix config channel addr
2017-05-22 17:45:14 +02:00
e845de2ff2
remove aqcli_pdq2
2017-05-22 19:17:23 +08:00
e4a631a3d7
scheduler: consider the pipeline flushed if everything has a lower priority than us. Closes #640
2017-05-22 18:43:59 +08:00
5fc953119e
fix usage of CommMgmt
2017-05-22 17:32:11 +08:00
6bdb76e9ea
core device logging controller WIP ( #691 )
2017-05-22 16:48:00 +08:00
5ccca74a3f
fold comm device into core device
2017-05-22 15:45:45 +08:00
e7382f4753
fix test_ctlmgr
2017-05-22 15:04:46 +08:00
0ae5e6d8b1
test_lda: more thorough and consistent test of simulation mode
2017-05-22 00:26:05 +08:00
3ed70afaa1
Use commandline prefix for controllers
...
This keeps them better organized and consistent with the artiq_* naming scheme.
Tab completion from aqctl_ also lists all the controllers installed on a machine.
2017-05-22 00:22:10 +08:00
c83e15d040
artiq_corelog: cleanup
2017-05-22 00:06:03 +08:00
8cf0628435
fix lit tests
2017-05-18 23:41:01 +08:00
b7a94d466d
fix experiment name conflict in phaser example
2017-05-18 23:14:55 +08:00
cd757c0f16
generate device database from executable python file
2017-05-18 23:14:55 +08:00
Florent Kermarrec
db3e1aef77
examples/phaser: adapt test_ad9154_prbs to new prbs in fabric
2017-05-15 16:12:02 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
ad85a0cee3
add session manager ( #691 )
2017-05-15 17:05:22 +08:00
0b6fb95deb
firmware: fix revision of compiler_builtins for satman
2017-05-13 15:12:53 +01:00
170d2886fd
Merge branch 'pdq'
...
* pdq:
pdq: documentation
pdq2 -> pdq
pdq2: use 16 bit data, buffered read_mem()
spi: style
pdq2: mem_read
pdq2: align subsequent writes to end
sma_spi: undo cri_con
pdq2: memory write, kernel_invariants
sma_spi: cri/cd changes
sma_spi: LVCMOS25
coredevice.spi: kernel invariants and style
sma_spi: free up user_sma pins
sma_spi: add demo target with SPI on four SMA
pdq2: memory write
pdq2: crc/frame register accessors
doc: pdq2 spi backend
pdq2: config writes
2017-05-12 11:46:45 +02:00
fed24309b8
pdq: documentation
2017-05-02 18:55:02 +02:00
1a1edb13bf
pdq2 -> pdq
2017-05-02 18:05:41 +02:00
Florent Kermarrec
79c339d4ac
gateware/targets/phaser: jesd core now handles jsync completely
2017-04-26 22:25:08 +02:00
8ebb33c05c
master: record time run() is called
2017-04-26 23:36:19 +08:00
Florent Kermarrec
0546affd4c
gateware/target/phaser: jesd start signal renamed to jsync
2017-04-26 12:27:40 +02:00
whitequark
bb64992395
compiler: remove dead code.
2017-04-21 18:38:43 +00:00
whitequark
c5d7445973
compiler: reject reachable implicit return if not returning TNone.
...
Fixes #718 .
2017-04-21 18:11:14 +00:00
whitequark
ed2b10c5aa
compiler: in codegen for delay(), round fp instead of truncating.
...
Consider delay(8*us). It results in the following computation...
>>> 8*1e-06/1e-09
7999.999999999999
with the result promptly getting truncated to 7999.
Fixes #706 .
2017-04-21 17:36:44 +00:00
whitequark
a820ae98cf
ksupport: avoid allocations on I/O error paths.
...
Fixes #715 .
2017-04-21 17:20:50 +00:00
whitequark
b913d1d6f2
runtime: make a copy of startup/idle kernel firmware before loading.
...
Fixes #716 .
2017-04-21 16:46:40 +00:00
whitequark
726ee7370a
runtime: update smoltcp.
...
This brings in correct TIME-WAIT handling. Fixes #722 .
2017-04-21 16:08:04 +00:00
whitequark
0e68eaa879
runtime: print a heap dump on out-of-memory condition.
2017-04-21 14:48:10 +00:00
whitequark
fd994ceef3
DMA: various fixes to bring tests in line.
2017-04-20 20:05:03 +00:00
whitequark
db494967c5
firmware use Rust 0.18.0.
2017-04-19 09:38:24 +00:00
fe05aede78
firmware: DmaPlayback → DMARetrieve
2017-04-19 11:11:42 +08:00
e8f7f8ef9c
DMA: speed up playback
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Time reduced from 1.53µs to 1.37µs.
2017-04-19 10:59:12 +08:00
whitequark
41c4de4556
DMA: add API for a much faster replay using handles.
2017-04-18 08:20:12 +00:00
whitequark
c6e8d5c901
runtime: allow setting UART log level explicitly.
...
This is way more convenient than commenting out parts
of session.rs when debugging.
2017-04-15 08:27:18 +00:00
whitequark
0531dc45c3
DMA: erase trace before re-recording it.
...
Or we could needlessly OOM replacing a large trace.
2017-04-15 07:48:02 +00:00
whitequark
9dfe9c1248
DMA: improve recording performance.
...
This commit moves DMA serialization code to the kernel CPU
(to cope with the existence of rtio_output_wide) and batches
the resulting sequences. This results in less data being transferred
between kernel and comms CPUs (24 octets with one pointer before,
18 octets with no pointers now, for the common case of rtio_output),
but most importantly reduces cache flushes, which now happen
once per 64k octets.
On average, it now takes about 15us to record a single RTIO event
in a DMA trace.
Fixes #712 .
2017-04-15 07:29:52 +00:00
whitequark
ea753bed17
runtime: advise to set panic_reboot=1 on panic.
2017-04-15 07:29:36 +00:00
534e681d0b
pdq2: use 16 bit data, buffered read_mem()
2017-04-13 20:49:46 +02:00
90cf11994e
spi: style
2017-04-13 13:38:29 +02:00
