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471 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq a8ecbd6041 firmware: do not attempt to build Si5324 code when gateware does not support it 2017-02-03 12:27:13 +08:00
Sebastien Bourdeauducq d181989de9 drtio: reset Si5324 at each boot 2017-02-03 12:00:58 +08:00
Sebastien Bourdeauducq b3697f951a drtio: forward clocks to SMA connectors for debugging 2017-02-03 12:00:36 +08:00
Sebastien Bourdeauducq aafefee7f5 targets: make number of ethmac slots consistent 2017-02-02 23:02:51 +08:00
whitequark 44a9a79f96 firmware: port allocator to Rust. 2017-02-02 10:55:35 +00:00
Sebastien Bourdeauducq f512ea42dc drtio: initialize si5324 in firmware 2017-02-02 18:11:24 +08:00
whitequark b95db4fa4e Use four ethmac buffers instead of two. 
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
 2017-01-30 07:42:27 +00:00
Sebastien Bourdeauducq 9800acea92 drtio: program Si5324 for 150MHz in 3G config 2017-01-30 14:50:12 +08:00
Sebastien Bourdeauducq 7daab07a29 drtio: fix syntax/import 2017-01-30 13:01:45 +08:00
Sebastien Bourdeauducq d8e9949266 drtio: initialize AD9516 clock chip 2017-01-30 11:06:45 +08:00
Sebastien Bourdeauducq f6024b6c9a drtio: fix ad9154 extension registration 2017-01-30 10:59:22 +08:00
Sebastien Bourdeauducq 43aad0914e python3.5 -> python3 
Many things also work with Python 3.6.
 2017-01-30 09:24:43 +08:00
Sebastien Bourdeauducq 657afd770e artiq/test/gateware -> artiq/gateware/test 
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
 2017-01-30 09:00:55 +08:00
Sebastien Bourdeauducq 94b0783897 drtio: remove support for transceiver SMAs 
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
 2017-01-27 23:33:50 +08:00
whitequark de17908b38 Revert "Globally update UART baudrate to 921600." 
This reverts commit b29e2d5bfe.

This broke flterm firmware upload, which was the entire point
of the whole exercise.
 2017-01-25 00:31:28 +00:00
whitequark b29e2d5bfe Globally update UART baudrate to 921600. 2017-01-24 22:25:58 +00:00
whitequark 527b1e986c firmware: integrate smoltcp instead of lwip. 2017-01-23 13:59:34 +00:00
Sebastien Bourdeauducq 28a41a2f60 gateware: fix aeb1ba847 2017-01-18 17:11:02 -06:00
Sebastien Bourdeauducq 2a7a8f91ca gateware: fix import 2017-01-18 16:51:30 -06:00
Sebastien Bourdeauducq ce31ffddb0 firmware: add satellite manager 
The code duplication with the runtime should be cleaned up later.
 2017-01-18 16:50:32 -06:00
Sebastien Bourdeauducq b40953800a gateware: soc -> amp.soc 2017-01-18 15:28:14 -06:00
Sebastien Bourdeauducq aeb1ba8471 gateware: use default MiSoC timer 2017-01-18 15:22:33 -06:00
Sebastien Bourdeauducq b8d89d56b1 drtio: add GenericRXSynchronizer 2017-01-15 13:44:43 -06:00
Sebastien Bourdeauducq 0edffb54c2 drtio: fix packet truncation detection in RTPacketSatellite 2017-01-13 09:29:22 -06:00
Sebastien Bourdeauducq 6805feb494 drtio: report truncated packets 2017-01-12 23:44:45 -06:00
Sebastien Bourdeauducq 7c699e2f80 drtio: add FIFO space request count debug API 2017-01-11 13:48:14 -06:00
Sebastien Bourdeauducq c25186fae1 drtio: print packet error descriptions in log 2017-01-10 18:03:01 -06:00
Sebastien Bourdeauducq 98598df78e rtio: keep retrying on get FIFO space timeout 2017-01-10 16:12:32 -06:00
Sebastien Bourdeauducq e624f45369 drtio: remove FIFO empty local detection optimization 
It optimizes a marginal case, it is difficult to get right
(need to know the size of the FIFO for each channel), and
it adds complexity and potential bug sources.
 2017-01-10 14:31:46 -06:00
Sebastien Bourdeauducq f75fffcf96 drtio: fix satellite RX data corruption 2017-01-10 14:29:30 -06:00
Sebastien Bourdeauducq fe53bab953 targets: kc705 -> kc705_dds 2017-01-05 18:40:56 +01:00
Sebastien Bourdeauducq 082fdaf450 move i2c to libboard, do bit-banging on comms CPU 2017-01-04 21:04:38 +01:00
Sebastien Bourdeauducq 86f6b391b7 ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
Sebastien Bourdeauducq c08fc8aae9 firmware: support moninj without DDS. Closes #650 2017-01-04 11:26:02 +01:00
Sebastien Bourdeauducq 455250b3f9 remove DDS_AD9914 and DDS_ONEHOT_SEL 2017-01-03 22:04:25 +01:00
Sebastien Bourdeauducq fbf5a4d4a2 Merge branch 'phaser2-rust-init' 2017-01-03 21:31:21 +01:00
Robert Jördens 9a80b8d533 spi: fix xfers with full data_width (closes #615) 
misoc 15000af43611bbe8be13cb2b016e408f043202cd
 2017-01-03 19:51:14 +01:00
Sebastien Bourdeauducq 7ff77bceac move AD9616 and AD9154 initialization to firmware 2017-01-03 16:11:38 +01:00
Sebastien Bourdeauducq 417708af90 phaser: add note about DDS defines (#650) 2017-01-02 22:15:21 +01:00
Robert Jördens f5f662200b fir: streamline, optimize DSP extraction, left-align inputs 2016-12-20 21:39:51 +01:00
Robert Jördens cfb66117af fir: size hint for pre-adder 2016-12-20 17:58:06 +01:00
Robert Jördens f310274e39 fir: cleanup halfgen4 2016-12-20 17:58:06 +01:00
Sebastien Bourdeauducq 6b998581cc rtio: use same reset for counter_rtio whatever the interface delay is 2016-12-15 09:28:13 +08:00
Robert Jördens 115ea67860 fir: automatically use transposed topology 2016-12-14 19:16:07 +01:00
Robert Jördens a451b675c9 Revert "fir: different adder layout" 
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
 2016-12-14 19:16:07 +01:00
Robert Jördens 93076b8efa fir: different adder layout 2016-12-14 19:16:07 +01:00
Robert Jördens 61abd994e9 Revert "fir: force dsp48" 
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
 2016-12-14 19:16:07 +01:00
Robert Jördens 641d109786 fir: force dsp48 2016-12-14 19:16:07 +01:00
Robert Jördens 8381db279f sawg: wire up all HBF outputs, latency compensation in phys, simplify 2016-12-14 19:16:07 +01:00
Robert Jördens 6cdb96c5e0 rtio: add support for latency compensation in phy 
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
 2016-12-14 19:16:07 +01:00