61 Commits

Author	SHA1	Message	Date
whitequark	38a99fde52	Implement selective attribute writeback using shadow memory.	2016-01-02 22:51:04 +08:00
whitequark	fd46690cf5	compiler: make IR dumps vastly more readable.	2015-11-17 00:23:34 +03:00
whitequark	5151adb9a8	compiler.targets: correctly pass CPU features to LLVM.	2015-08-30 16:56:58 -05:00
whitequark	edf33f1643	compiler.targets: dump module signature with ARTIQ_DUMP_SIG=1.	2015-08-28 02:22:35 -05:00
whitequark	d473d58b41	artiq_{compile,run}: adapt to new compiler.	2015-08-28 01:43:46 -05:00
whitequark	261515dfe5	compiler.targets.OR1KTarget: fix typo.	2015-08-10 15:47:44 +03:00
whitequark	75532d10aa	Display full core device backtraces.	2015-08-10 15:12:22 +03:00
whitequark	8b7d38d203	Add ARTIQ_DUMP_ASSEMBLY.	2015-08-09 15:47:29 +03:00
whitequark	9c5ca2ae29	LLVMIRGenerator: add target data layout to LLVM modules.	2015-08-09 14:39:21 +03:00
whitequark	aae2923c4c	runtime: add lognonl{,_va} functions. ... The kernels have print(), which prints aggregates (such as arrays) piece-by-piece, and newlines would interfere.	2015-08-02 06:33:12 +03:00
whitequark	e8943a008c	Rename compiler/{targets/__init__.py → targets.py}.	2015-07-30 10:35:04 +03:00