* coredevice: Change Urukul default single-tone profile to 7
This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.
Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>
* ad9910/set_mu: comment on caveats when setting register
* ad9910: avoid unnecessary write/param
Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353
* revert 1064fdff (`set_mu()` comments)
158a7be7 had addressed this issue.
Co-authored-by: occheung <dc@m-labs.hk>
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
When run on the host, the `turns_to_pow` retrun-type is numpy.int64.
Sensibly, the compiler does not attempt to convert `numpy.int64` to `int32`.
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* coredevice.ad9910: Add return type hints to conversion functions
* coredevice.ad9910: Make set_pow write correct number of bits
The AD9910 expects 16 bits. Thus, if writing 32 bits to the POW register, the chip would likely enter a locked-up state.
* coredevice.ad9910: Correct data alignment in write_16
Co-authored-by: Robert Jördens <rj@quartiq.de>
* coredevice.ad9910: Add function to read from 16 bit registers
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
* ad9910: fix asf range
The ASF is a 14-bit word. The highest possible value is 0x3fff, not
0x3ffe. `int(round(1.0 * 0x3fff)) == 0x3fff`.
I don't remember and understand why this was 0x3ffe since the beginning.
0x3fff was already used as a default in `set_mu()`
Signed-off-by: Robert Jördens <rj@quartiq.de>
* RELEASE_NOTES: ad9910 asf scale change
Co-authored-by: David Nadlinger <code@klickverbot.at>
* Input validation and masking of SI -> mu conversions (close#1446)
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* Update RELEASE_NOTES
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
* updated adoo10.py for RAM mode frequency control
* updated docstrings for set_cfr1() in ad9910.py
* fixed typo in ad9910.py
* added docstrings to ad9910.py
* removed OSK-related changes in AD9910, to be included in a separate branch.
* updated AD9910 set_cfr1 for control of OSK mode parameters
* updated AD9910 set_cfr1() for control of OSK mode parameters.
This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).
This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.
close#1229
Signed-off-by: Robert Jördens <rj@quartiq.de>
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP
Found while building docs. Forgot to refactor strings.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
* spi2: reformat update_xfer_duration_mu docstring
update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
Norman Krackow
occheung
Peter Drmota
Leon Riesebos
Sebastien Bourdeauducq
Marius Weber
Robert Jördens
gthickman
Fabian Schmid
Garrett
Tim Ballance
David Nadlinger
Drew