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mirror of https://github.com/m-labs/artiq.git synced 2024-12-23 02:14:01 +08:00
Commit Graph

5445 Commits

Author SHA1 Message Date
whitequark
8f2dfcd08e Rename conda package llvmlite-{or1k → artiq}. 2015-08-05 04:17:59 +03:00
whitequark
4a8e397a77 Fold llvmlite patches into m-labs/llvmlite repository. 2015-08-05 03:49:01 +03:00
whitequark
d0402243a0 Update installation instructions. 2015-08-04 18:00:10 +03:00
18f38e6242 doc/manual: make sure correct Clang is used 2015-08-04 20:20:56 +08:00
433cb948bc doc: artiq git clone needs --recursive to fetch lwIP 2015-08-04 17:01:12 +08:00
whitequark
ad7cbc4394 Rename artiq_coreconfig → artiq_coretool; add log subcommand. 2015-08-02 16:40:58 +03:00
whitequark
8d0222c297 Rename artiq_coreconfig → artiq_coretool; add log subcommand. 2015-08-02 16:40:43 +03:00
whitequark
62fdc75d2d Integrate libdyld and libunwind.
It is currently possible to run the idle experiment, and it
can raise and catch exceptions, but exceptions are not yet
propagated across RPC boundaries.
2015-08-02 15:43:03 +03:00
whitequark
6db93b34e8 artiq_personality: port to device. 2015-08-02 06:34:11 +03:00
whitequark
aae2923c4c runtime: add lognonl{,_va} functions.
The kernels have print(), which prints aggregates (such as
arrays) piece-by-piece, and newlines would interfere.
2015-08-02 06:33:12 +03:00
whitequark
cd294e2986 artiq_personality: avoid unaligned loads. 2015-08-02 06:28:58 +03:00
b2f720da67 gui: better state error handling
Remains limited by issue pyqtgraph/pyqtgraph#204
2015-08-01 19:52:13 +08:00
8ad88438c7 gui: save display state 2015-08-01 19:37:16 +08:00
a64766a10d protocols/FlatFileDB: remove unneeded default_data 2015-08-01 16:49:05 +08:00
00cae1c23a gui: save dock area state 2015-08-01 16:48:44 +08:00
9e24b56099 gui: add state manager 2015-08-01 16:48:27 +08:00
4a7a4acf07 conda: remove unnecessary pixman package 2015-08-01 00:16:26 +08:00
9b0ed344ed runtime/Makefile: WA for more pesky travis/miniconda misbehavior 2015-07-31 19:29:34 +08:00
89343ae276 examples/speed_benchmark: send 1MB in one RPC 2015-07-31 18:23:11 +08:00
whitequark
33531c2f3b Rename {kserver → net_server}.{c,h}. 2015-07-31 18:18:25 +08:00
8d1663394b runtime: increase lwip TCP_SND_QUEUELEN (closes #82) 2015-07-31 18:16:02 +08:00
d02d40871e runtime: update lwip 2015-07-31 18:15:16 +08:00
b4e1d1b074 conda/artiq: use $PYTHON 2015-07-31 15:03:54 +08:00
a118d03ac6 even more travis debugging 2015-07-31 14:57:26 +08:00
feb2c4d0c4 more travis debugging 2015-07-31 14:52:15 +08:00
36d92c72df travis: try export 2015-07-31 14:10:14 +08:00
53f55a7502 try to workaround travis problem 2015-07-31 14:01:39 +08:00
f3c38005d3 i hate travis-ci 2015-07-31 13:58:28 +08:00
4df2001874 travis: try to use the new anaconda-client 2015-07-31 13:50:35 +08:00
whitequark
697b78ddf2 Rename {kserver → net_server}.{c,h}. 2015-07-30 13:45:57 +03:00
whitequark
e8943a008c Rename compiler/{targets/__init__.py → targets.py}. 2015-07-30 10:35:04 +03:00
whitequark
1e3911ed39 Use try..finally in compiler.targets.Target.link. 2015-07-30 10:33:54 +03:00
whitequark
b0185f3917 Add profiling to the performance testbench. 2015-07-29 22:23:22 +03:00
whitequark
d7f9af4bb5 Fix accidentally quadratic code in compiler.ir.Function._add_name. 2015-07-29 21:36:31 +03:00
whitequark
6d8d0ff3f5 Update performance testbench to include time spent in ARTIQ. 2015-07-29 21:28:07 +03:00
whitequark
3b5d3e2b1a Add a performance measurement testbench. 2015-07-29 21:17:52 +03:00
55708e8678 pipistrello: drop bitgen_opt change (done upstream) 2015-07-29 11:45:15 -06:00
whitequark
e8c107925c Implement shared object linking. 2015-07-29 20:35:16 +03:00
6b98f867de import DDS phase modes at the top level 2015-07-29 23:32:33 +08:00
1ddb19277f add speed benchmark 2015-07-29 23:29:26 +08:00
86fef7b53b master: do not scan experiments starting with '_' 2015-07-29 23:29:07 +08:00
a8c13cb7de gui: fix NumberEntry min/max 2015-07-29 23:28:34 +08:00
1d34c06d79 rtio: detect collision errors 2015-07-29 19:43:35 +08:00
b548d50a2f test/coredevice: use ttl_out for PulseRate (loop is less available) 2015-07-29 19:42:43 +08:00
whitequark
2cd25f85bf Rename artiq.compiler.testbench.{module → signature}. 2015-07-29 14:32:34 +03:00
whitequark
3378dd57b8 Fold llvmlite patches into m-labs/llvmlite repository. 2015-07-29 13:54:00 +03:00
whitequark
fd46d8b11e Merge branch 'master' into new-py2llvm 2015-07-29 12:52:19 +03:00
whitequark
c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
ebbbdcf194 examples/tdr: cleanup 2015-07-28 23:30:26 -06:00
278570faf6 examples: add TDR toy example 2015-07-28 21:36:10 -06:00